Altera MAX 10 FPGA Instrukcja Użytkownika Strona 47
- Strona / 56
- Spis treści
- BOOKMARKI
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Altera Corporation 3
- Configuration Scheme 4
- Remote System 4
- Features 5
- Internal Configuration 6
- Configuration Flash Memory 7
- In-System Programming 8
- UG-M10CONFIG 10
- 2015.05.04 10
- Configuration Features 12
- Remote System Upgrade Flow 13
- Bits Name Description 17
- Values State Description 17
- User Watchdog Timer 18
- Configuration Design Security 19
- Unique Chip ID 20
- JTAG Secure Mode 20
- Verify Protect 21
- JTAG Instruction Availability 21
- Configuration Error Detection 23
- User Mode Error Detection 23
- Error Detection Timing 24
- Recovering from CRC Errors 26
- Configuration Details 27
- Power Up 28
- MAX 10 Configuration Pins 29
- JTAG Pin Sharing Behavior 30
- Pins Guidelines 31
- Enabling Dual-purpose Pin 32
- JTAG Configuration Setup 33
- Related Information 34
- .pof and ICB Settings 35
- Auto-Generated .pof 36
- Error Detection 38
- Enabling Error Detection 39
- Enabling Data Compression 40
- AES Encryption 41
- Send Feedback 46
- Key Y Key Y Enabled image 0 47
- Implementation Guides 48
- Offset R/W Width 50
- Description 50
- Parameter Value Description 52
- Configuration User Guide 54
- Date Version Changes 55
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