Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Instrukcja Użytkownika Pobierz pdf (Strona 635)

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101

VHDL Tutorials

Verifying a Slave DUT

Mentor VIP AE AXI3/4 User Guide, V10.2b

615

September 2013

Example 11-8. m_rd_data_phase_ready_delay

-- Variable : m_rd_data_phase_ready_delay

signal m_rd_data_phase_ready_delay : integer := 2;

Configuration and Initialization

The Master Test process creates and executes read and write transactions. The whole process

runs concurrently with other processes in the test program, using the path_id = AXI4_PATH_0

(see Overloaded Procedure Common Arguments for details of path_id).

The process waits for the ARESETn signal to be deasserted, followed by a positive ACLK edge,

as shown in Example 11-10. This satisfies the protocol requirements in section A3.1.2 of the

AXI Protocol Specification.

Example 11-9. Configuration and Initialization

-- Master test

process

variable tr_id: integer;

variable data_words : std_logic_vector(AXI4_MAX_BIT_SIZE-1 downto 0);

variable lp: line;

begin

wait_on(AXI4_RESET_0_TO_1, index, axi4_tr_if_0(index));

wait_on(AXI4_CLOCK_POSEDGE, index, axi4_tr_if_0(index));

Write Transaction Creation and Execution

To generate AXI4-Lite protocol traffic, the Master Test Program must create a transaction

before executing it. The code shown in Example 11-10 calls the create_write_transaction()

procedure, providing only the start address argument of the transaction. The optional burst-

length argument automatically defaults to a value of zero—indicating a burst length of a single

beat.

This example has an AXI4 write data bus width of 32-bits; therefore a single beat of data

conveys 4-bytes across the data bus. The call to the set_data_words() procedure sets the first

element of the data_words[0] transaction field with the value 1 on byte lane 1, with result of

x”0000_0100”. However, the AXI4 protocol permits narrow transfers with the use of the write

strobes signal WSTRB to indicate which byte lane contains valid write data, and therefore

indicates to the slave DUT which data byte lane will be written into memory. The write strobes

WSTRB signal indicates to the slave which byte lane contains valid write data to be written to

the slave memory. Similarly, you can call the set_write_strobes() procedure to set the first

element of the write_strobes transaction field with the value 2, indicating that only byte lane 1

contains valid data. Calling the execute_transaction() procedure executes the transaction on the

protocol signals

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