Altera 100G Development Kit, Stratix IV GT Edition Instrukcja Użytkownika Pobierz pdf (Strona 23)

Chapter 2: Board Components 2–15

MAX II CPLD EPM2210 System Controller

September 2010 Altera Corporation 100G Development Kit, Stratix IV GT Edition Reference Manual

U72.N17

Spare I/Os on the MAX II device and

is designed as an I/O expander for

the FPGA. Data can be passed

through the MAX_STRATIX

interface.

Bidirectional

LINE_SIDE0

—J48.1

U72.M13 Bidirectional

LINE_SIDE1

—J48.3

U72.N18 Bidirectional

LINE_SIDE2

—J48.5

U72.M12 Bidirectional

LINE_SIDE3

—J48.7

U72.M16 Bidirectional

LINE_SIDE4

—J48.9

U72.L16 Bidirectional

LINE_SIDE5

— J48.11

U72.M17 Bidirectional

LINE_SIDE6

— J48.13

U72.L15 Bidirectional

LINE_SIDE7

— J48.15

U72.M18 Bidirectional

LINE_SIDE8

— J48.17

U72.L14 Bidirectional

LINE_SIDE9

— J48.19

U72.M5

Initiates a load of the selected image

from the PFL

Input

LOAD

— S11.2

U72.R16

Control signal between the MAX II

system controller and the MAX II

embedded USB-Blaster to indicate

that configuration is done.

Input

MAX_2_MAX_INITD

ONE

—U80.J6

U72.T16

FPGA configuration done LED.

Indicates that the FPGA is loaded

with the new image.

Output

MAX_CONF_DONEn

— D37.2

U72.T17 FPGA configuration error LED Output

MAX_ERROR

— D38.2

U72.R15 FPGA configuration active LED Output

MAX_LOAD

— D36.2

U72.V10 FPGA to MAX II I/O expander

address bus

Input

MAX_STRATIX_A0

U44.AN34 —

U72.P10 Input

MAX_STRATIX_A1

U44.AN33 —

U72.U11 Input

MAX_STRATIX_A2

U44.AT39 —

U72.R10 Input

MAX_STRATIX_A3

U44.AU39 —

U72.T15 FPGA to MAX II I/O expander data

bus

Bidirectional

MAX_STRATIX_D0

U44.AF38 —

U72.R12 Bidirectional

MAX_STRATIX_D1

U44.W38 —

U72.V14 Bidirectional

MAX_STRATIX_D2

U44.AG31 —

U72.P12 Bidirectional

MAX_STRATIX_D3

U44.AK39 —

U72.T13

MAX_STRATIX interface ready

indicator

Input

MAX_STRATIX_RDY

U44.AU37 —

U72.V17

Read-write signal for

MAX_STRATIX interface.

Control signal from the FPGA to

indicate that the FPGA is accessing

the flash in BYTE mode.

Input

MAX_STRATIX_RW

U44.AU36 —

U72.C17

Over-temperature indicator from the

temperature sense circuit

Input

OVERTEMPn

—

U70.4, D18.2,

D42.2

U72.N1

Push-button to select which image

to program into the FPGA

Input

PGM_SEL

— S10.2

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 4 of 6)

EPM2210

Pin Number

Description Type

Schematic Signal

Name

Stratix IV

GT Device

Pin Name

Other

Connections

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 79 80

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