
Chapter 2: Board Components 2–59
Components and Interfaces
September 2010 Altera Corporation 100G Development Kit, Stratix IV GT Edition Reference Manual
U48.A5 Byte write select
QDR2B_BWSN1
U44.BD14 —
U48.A1 QDR II echo clock
QDR2B_CQ_N
U44.AR19 —
U48.A11 QDR II echo clock
QDR2B_CQ_P
U44.AM19 —
U48.P10 Write data bus
QDR2B_D0
U44.AW19 —
U48.N11 Write data bus
QDR2B_D1
U44.AY19 —
U48.M11 Write data bus
QDR2B_D2
U44.AW18 —
U48.K10 Write data bus
QDR2B_D3
U44.BA19 —
U48.J11 Write data bus
QDR2B_D4
U44.BA18 —
U48.G11 Write data bus
QDR2B_D5
U44.AW17 —
U48.E10 Write data bus
QDR2B_D6
U44.BB18 —
U48.D11 Write data bus
QDR2B_D7
U44.BA17 —
U48.C11 Write data bus
QDR2B_D8
U44.BD18 —
U48.B3 Write data bus
QDR2B_D9
U44.AW15 —
U48.C3 Write data bus
QDR2B_D10
U44.AW16 —
U48.D2 Write data bus
QDR2B_D11
U44.BB15 —
U48.F3 Write data bus
QDR2B_D12
U44.BA15 —
U48.G2 Write data bus
QDR2B_D13
U44.BC16 —
U48.J3 Write data bus
QDR2B_D14
U44.BA16 —
U48.L3 Write data bus
QDR2B_D15
U44.BD17 —
U48.M3 Write data bus
QDR2B_D16
U44.BC17 —
U48.N2 Write data bus
QDR2B_D17
U44.BB17 —
U48.A6 QDR II clock input
QDR2B_K_N
U44.AY17 —
U48.B6 QDR II clock input
QDR2B_K_P
U44.AY16 —
U48.P11 Read data bus
QDR2B_Q0
U44.AJ20 —
U48.M10 Read data bus
QDR2B_Q1
U44.AK20 —
U48.L11 Read data bus
QDR2B_Q2
U44.AL19 —
U48.K11 Read data bus
QDR2B_Q3
U44.AM18 —
U48.J10 Read data bus
QDR2B_Q4
U44.AN19 —
U48.F11 Read data bus
QDR2B_Q5
U44.AN18 —
U48.E11 Read data bus
QDR2B_Q6
U44.AP19 —
U48.C10 Read data bus
QDR2B_Q7
U44.AN17 —
U48.B11 Read data bus
QDR2B_Q8
U44.AP17 —
U48.B2 Read data bus
QDR2B_Q9
U44.AU16 —
U48.D3 Read data bus
QDR2B_Q10
U44.AV16 —
U48.E3 Read data bus
QDR2B_Q11
U44.AT17 —
U48.F2 Read data bus
QDR2B_Q12
U44.AU17 —
U48.G3 Read data bus
QDR2B_Q13
U44.AR16 —
U48.K3 Read data bus
QDR2B_Q14
U44.AT18 —
Table 2–39. QDR II Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 8)
Board
Reference
Description
Schematic
Signal Name
Stratix IV GT
Device
Pin Name
Other
Connections
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