Altera 100G Development Kit, Stratix IV GT Edition Instrukcja Użytkownika Strona 72

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2–64 Chapter 2: Board Components
Components and Interfaces
100G Development Kit, Stratix IV GT Edition Reference Manual September 2010 Altera Corporation
Ethernet RGMII Interface
The Stratix IV GT 100G development board incorporates a triple speed 10/100/1000
Base-T Ethernet RGMII interface.
The implementation uses an auto-negotiating Marvell 88E1111 Ethernet PHY (U66)
with an RGMII interface to the FPGA and interfaces to an RJ-45 connector (J49) with
internal magnetics that can be used for driving copper lines with Ethernet traffic.
Figure 2–11 shows the RGMII interface between the FPGA and Marvell 88E1111 PHY.
Table 241 shows the Ethernet RGMII interface pin connection to the FPGA for the
Ethernet PHY.
Figure 2–11. Ethernet RGMII Interface
Stratix IV GT
FPGA
(U44)
RGMII
Marvell 88E1111
Ethernet PHY
(U66)
TX/RX
RJ45
Connector (J49)
Table 2–41. Ethernet RGMII Interface Pin Assignments, Signal Names and Functions (Part 1 of 2)
Board
Reference
Description
Schematic Signal
Name
I/O Standard
Stratix IV GT
Device Pin
Number
Other
Connections
U66.28 Ethernet reset
ENET_RESETn
LVCMOS
AV35
U66.24 Ethernet management bus data
ENET_MDIO
AV38
U66.25 Ethernet management bus control
ENET_MDC
AJ32
U66.8 Ethernet clock
ENET_GTX_CLK
AP37
U66.9 Ethernet transmit enable
ENET_TX_EN
AJ31
U66.94 Ethernet receive data valid
ENET_RX_DV
AV37
U66.11 Ethernet transmit data
ENET_TXD0
AK31
U66.12 Ethernet transmit data
ENET_TXD1
AK32
U66.14 Ethernet transmit data
ENET_TXD2
AW36
U66.16 Ethernet transmit data
ENET_TXD3
AW37
U66.95 Ethernet receive data
ENET_RXD0
AR35
U66.92 Ethernet receive data
ENET_RXD1
AT36
U66.93 Ethernet receive data
ENET_RXD2
AU34
U66.91 Ethernet receive data
ENET_RXD3
AT34
U66.2 Ethernet receive clock
ENET_RX_CLK
U39
U66.31 Media dependent interface 0 (N)
MDI_N0
J49.2
U66.29 Media dependent interface 0 (P)
MDI_P0
J49.1
U66.34 Media dependent interface 1 (N)
MDI_N1
J49.6
U66.33 Media dependent interface 1 (P)
MDI_P1
J49.3
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