Altera ALTDLL Instrukcja Użytkownika Pobierz pdf (Strona 52)

Chapter 4: Functional Description 4–16

Delay Chains

Deskew Delay Chains

The deskew delay chain feature in Stratix III or Stratix IV devices is useful in external

memory interfaces, such as DDR or DDR2 external memory interfaces. Refer to

Figure 4–8.

This feature is useful in deskewing the DQ bus for board trace mismatches between

the FPGA and external memory interface.

The graph on the left is obtained when no deskew delay chains are used. The capture

window is small because of the board trace delays.

The graph on the right is obtained when deskew delay chains are used to deskew the

DQ bus appropriately, based on the board trace delays, to maximize the capture

window.

The deskew delay chains reduce SSN by delaying the DQ bus by small amounts of

delay compared to the period of the signal on adjacent DQ pins. Refer to Figure 4–8.

Figure 4–8. Deskew Delay Chains

105

120

135

150

165

180

dq0

dq1

dq2

dq3

dq4

dq5

dq6

dq7

Incoming DQS

strobe phase

Prior to de-skew - small valid capture window

Incoming DQ

data bus

DQS

105

120

135

150

165

180

dq0

dq1

dq2

dq3

dq4

dq5

dq6

dq7

DQS

After de-skew - maximize valid capture window

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