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Chapter 4: Functional Description 4–40

ALTDQ_DQS Megafunction Ports

DQ Output Path Megafunction Ports

Table 4–16 summarizes all the ports on the megafunction that configure the DQ

Output path. The possible values for <IO> are BIDIR_DQ and OUTPUT_DQ.

Table 4–16. Megafunction Ports to Configure DQ Output Path (Part 1 of 2)

Port Name Type

Optional/

Required Default Description

bidir_dq_areset

-1..0]

Input Optional GND This port is connected to all areset ports in the

bidirectional DQ IO primitives that is used to

asynchronously reset the registers in those

primitives.

bidir_dq_hr_output_dat

a_in[4*n

-1..0]

Input Optional GND This port feeds the half-rate DDR bidirectional DQ

signal for the

BIDIR_DQ_OUTPUT_HR_DDIO_OUT_HIGH:

datainhi / datainlo and

BIDIR_DQ_OUTPUT_HR_DDIO_OUT_LOW:d

atainhi / datainlo ports.

bidir_dq_output_data_i

n [n

-1..0]

Input Optional GND This port feeds the bidirectional DQ signal for the

BIDIR_DQ_OUTPUT_FF:d,

BIDIR_DQ_OUTPUT_DELAY_CHAIN1:data

in,

BIDIR_DQ_OUTPUT_DELAY_CHAIN2:data

in, or bidir_dq_output_data_out port

bidir_dq_output_data_i

n_high[n

-1..0]

Input Optional GND This port feeds the full-rate DDR bidirectional DQ

signal (rising edge) for the

BIDIR_DQ_OUTPUT_DDIO_OUT:datainhi

port.

bidir_dq_output_data_i

n_low[n

-1..0]

Input Optional GND This port feeds the full-rate DDR bidirectional DQ

signal (falling edge) for the

BIDIR_DQ_OUTPUT_DDIO_OUT:datainlo

port.

bidir_dq_output_data_

out[n

-1..0]

Output Optional — This port outputs the bidirectional DQ signal from

the

BIDIR_DQ_OUTPUT_DELAY_CHAIN2:data

out,

BIDIR_DQ_OUTPUT_DELAY_CHAIN1:data

out, BIDIR_DQ_OUTPUT_FF:q,

BIDIR_DQ_OUTPUT_DDIO_OUT:dataout,

or bidir_dq_output_data_in port.

bidir_dq_sreset

-1..0]

Input Optional GND This port is connected to all sreset port in the

bidirectional DQ IO primitives that is used to

synchronously reset the registers in those

primitives.

dq_hr_output_reg_clk Input Optional GND This port feeds the output enable signal for the

<IO>_OUTPUT_FF:ena and

<IO>_OUTPUT_DDIO_OUT:ena ports.

dq_output_reg_clk Input Optional GND This port feeds the clock signal for the

<IO>_OUTPUT_FF:clk and

<IO>_OUTPUT_DDIO_OUT:clkhi / clklo /

muxsel ports.

1 2 ... 71 72 73 74 75 76 77 78 79 80 81 ... 116 117

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