Altera Arria II GX FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 16)

2–8 Chapter 2: Board Components

MAX II CPLD EPM2210 System Controller

Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation

clk1_od[0]

2.5-V

M2 — Programmable oscillator 1 output divider 0

clk1_od[1]

M1 — Programmable oscillator 1 output divider 1

clk1_od[2]

L3 — Programmable oscillator 1 output divider 2

clk1_os[0]

N1 — Programmable oscillator 1 output select 0

clk1_os[1]

N2 — Programmable oscillator 1 output select 1

clk1_pr[0]

L2 — Programmable oscillator 1 prescaler 0

clk1_pr[1]

L1 — Programmable oscillator 1 prescaler 1

clk1_rstn

M3 — Programmable oscillator 1 reset

clk100_cpld

H12 — 100 MHz clock input

clk155_oe

E1 — 155.52 MHz oscillator enable

clk2_ce

M14 — Programmable oscillator 2 chip select

clk2_od[0]

N16 — Programmable oscillator 2 output divider 0

clk2_od[1]

N14 — Programmable oscillator 2 output divider 1

clk2_od[2]

N13 — Programmable oscillator 2 output divider 2

clk2_os[0]

M15 — Programmable oscillator 2 output select 0

clk2_os[1]

M16 — Programmable oscillator 2 output select 1

clk2_pr[0]

P15 — Programmable oscillator 2 prescaler 0

clk2_pr[1]

P14 — Programmable oscillator 2 prescaler 1

clk2_rstn

N15 — Programmable oscillator 2 reset

csense_adc_f0

G16 — Power monitor frequency

csense_csn[0]

J14 — Power monitor 0 chip select

csense_csn[1]

H15 — Power monitor 1 chip select

csense_sck

H16 —

Power monitor serial peripheral interface (SPI)

clock

csense_sdi

H14 — Power monitor SPI data in

csense_sdo

H13 — Power monitor SPI data out

ddr2_scl

M7 — DDR2 SODIMM EEPROM clock

ddr2_sda

M6 — DDR2 SODIMM EEPROM data

ep_clk

J15 — EEPROM clock

ep_cs

J16 — EEPROM chip select

ep_di

K15 — EEPROM data in

ep_do

K16 — EEPROM data out

factory_user

L13 — Load factory or user design at power-up

flash_advn

C8 T4 FSM bus flash memory address valid

flash_cen

F15 M3 FSM bus flash memory chip enable

flash_clk

C9 N4 FSM bus flash memory clock

flash_oen

E7 K5 FSM bus flash memory output enable

flash_rdy_bsyn

D8 R3 FSM bus flash memory ready

flash_resetn

D15 N3 FSM bus flash memory reset

Table 2–7. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 5)

Schematic Signal Name I/O Standard

EPM2210

Pin Number

EP2AGX125

Pin Number

Description

1 2 ... 11 12 13 14 15 16 17 18 19 20 21 ... 63 64

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