Altera Arria II GX FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 29)

Chapter 2: Board Components 2–21

Clock Circuitry

February 2011 Altera Corporation Arria II GX FPGA Development Board Reference Manual

Clock Circuitry

This section describes the board's clock inputs and outputs.

Arria II GX FPGA Clock Inputs

The development board has two types of clock inputs—global clock inputs and

transceiver reference clock inputs.

Figure 2–6 shows the Arria II GX FPGA development board clock inputs.

Table 2–20 shows the external clock inputs for the Arria II GX FPGA development

board.

Figure 2–6. Arria II GX FPGA Development Board Clock Inputs

Q0Q1Q2Q3

3B 3A 4A 4B

8B 8A 7A 7B

6B 6A 5A 5B

PLL 1

PLL 2 PLL 3

PLL 4

EP2AGX125EF35

Control signals route

to MAX II

155.52 M

CLK_SEL

REFCLK INPUT

SMA SMA

(LVPECL)

2-to-4 buffer

MAX II CPLD

EPM2210 System Controller

25 MHz

Crystal

3.3V

Low Jitter Clock

Generator*

(Default 125 MHz)

CDCM61004RHB

XIN 2

(LVDS)

CLK1_RSTn

CLK1_CE

CLK1_OS1

CLK1_OS0

CLK1_PR1

CLK1_PR0

CLK1_OD2

CLK1_OD1

CLK1_OD0

3.3V

(LVPECL)

CLK 2 _ RSTn

CLK 2 _ CE

CLK 2 _ OS 1

CLK 2 _ OS 0

CLK 2_PR 1

CLK 2_PR 0

CLK 2_OD 2

CLK 2_OD 1

CLK 2_OD 0

3.3V

PCIE_REFCLK_P/N

XIN 1

7 6 5 4 3 2 1 07 6 5 4 3 2 1 0

HSMA_CLK_IN_P[1]/N[1]

(LVDS)

HSMA

CLK_IN_P[2]/N[2]

(LVDS)

HSMB_CLK_IN0

HSMA_CLK_IN0

* CDCM6100x can be set to output frequencies

of 100 MHz, 125 MHz, 156.25 MHz.

PLL

25 MHz

Crystal

CLK_IN_TOP_P/N

CLK_IN_BOT_P/N

CLOCK_SMA

SMA

100 M50 M

ENET_RX_CLK

(2.5 V)

Low Jitter Clock

Generator*

(Default 100 MHz)

CDCM61001RHB

(2.5 V) (2.5 V)

(LVDS)

Table 2–20. Arria II GX FPGA Development Board Clock Inputs (Part 1 of 2)

Source Schematic Signal Name Pin I/O Standard Description

U25

CLK_155_P R29

LVPECL

155.52 MHz oscillator which drives the

transceiver Q2 reference clock input with

100  OCT.

CLK_155_N R30

1 2 ... 24 25 26 27 28 29 30 31 32 33 34 ... 63 64

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