Altera Arria II GX FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 42)

2–34 Chapter 2: Board Components

Components and Interfaces

Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation

J2.47 LVDS TX bit 0 or CMOS bit 4

HSMA_TX_D_P0

LVDS or 2.5-V

AA10

J2.48 LVDS RX bit 0 or CMOS bit 5

HSMA_RX_D_P0

AC5

J2.49 LVDS TX bit 0n or CMOS bit 6

HSMA_TX_D_N0

AA9

J2.50 LVDS RX bit 0n or CMOS bit 7

HSMA_RX_D_N0

AC4

J2.53 LVDS TX bit 1 or CMOS bit 8

HSMA_TX_D_P1

Y11

J2.54 LVDS RX bit 1 or CMOS bit 9

HSMA_RX_D_P1

AE4

J2.55 LVDS TX bit 1n or CMOS bit 10

HSMA_TX_D_N1

Y10

J2.56 LVDS RX bit 1n or CMOS bit 11

HSMA_RX_D_N1

AF4

J2.59 LVDS TX bit 2 or CMOS bit 12

HSMA_TX_D_P2

AH2

J2.60 LVDS RX bit 2 or CMOS bit 13

HSMA_RX_D_P2

AF1

J2.61 LVDS TX bit 2n or CMOS bit 14

HSMA_TX_D_N2

AH1

J2.62 LVDS RX bit 2n or CMOS bit 15

HSMA_RX_D_N2

AG1

J2.65 LVDS TX bit 3 or CMOS bit 16

HSMA_TX_D_P3

AB10

J2.66 LVDS RX bit 3 or CMOS bit 17

HSMA_RX_D_P3

AE2

J2.67 LVDS TX bit 3n or CMOS bit 18

HSMA_TX_D_N3

AB9

J2.68 LVDS RX bit 3n or CMOS bit 19

HSMA_RX_D_N3

AE1

J2.71 LVDS TX bit 4 or CMOS bit 20

HSMA_TX_D_P4

J2.72 LVDS RX bit 4 or CMOS bit 21

HSMA_RX_D_P4

AC1

J2.73 LVDS TX bit 4n or CMOS bit 22

HSMA_TX_D_N4

J2.74 LVDS RX bit 4n or CMOS bit 23

HSMA_RX_D_N4

AD1

J2.77 LVDS TX bit 5 or CMOS bit 24

HSMA_TX_D_P5

AF3

J2.78 LVDS RX bit 5 or CMOS bit 25

HSMA_RX_D_P5

AB2

J2.79 LVDS TX bit 5n or CMOS bit 26

HSMA_TX_D_N5

AF2

J2.80 LVDS RX bit 5n or CMOS bit 27

HSMA_RX_D_N5

AB1

J2.83 LVDS TX bit 6 or CMOS bit 28

HSMA_TX_D_P6

AD4

J2.84 LVDS RX bit 6 or CMOS bit 29

HSMA_RX_D_P6

J2.85 LVDS TX bit 6n or CMOS bit 30

HSMA_TX_D_N6

AE3

J2.86 LVDS RX bit 6n or CMOS bit 31

HSMA_RX_D_N6

AA1

J2.89 LVDS TX bit 7 or CMOS bit 32

HSMA_TX_D_P7

J2.90 LVDS RX bit 7 or CMOS bit 33

HSMA_RX_D_P7

J2.91 LVDS TX bit 7n or CMOS bit 34

HSMA_TX_D_N7

J2.92 LVDS RX bit 7n or CMOS bit 35

HSMA_RX_D_N7

J2.95 LVDS or CMOS clock out 1 or CMOS bit 36

HSMA_CLKOUT_P1

AD7

J2.96 LVDS or CMOS clock in 1 or CMOS bit 37

HSMA_CLKIN_P1

J2.97 LVDS or CMOS clock out 1 or CMOS bit 38

HSMA_CLKOUT_N1

AD6

J2.98 LVDS or CMOS clock in 1 or CMOS bit 39

HSMA_CLKIN_N1

J2.101 LVDS TX bit 8 or CMOS bit 40

HSMA_TX_D_P8

AA7

J2.102 LVDS RX bit 8 or CMOS bit 41

HSMA_RX_D_P8

Table 2–37. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference

Description

Schematic Signal

Name

I/O Standard

Arria II GX

Device

Pin Number

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 63 64

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Altera Arria II GX FPGA Development Board Instrukcja Użytkownika Strona 42

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