Altera DDR SDRAM Controller Instrukcja Użytkownika Pobierz pdf (Strona 53)

Chapter 3: Functional Description 3–17

Device-Level Description

Figure 3–12 shows the testbench and the example design.

1 Ensure that the example driver is not optimized away in your example design, by

preserving the pnf output. Either attach it to a pin or assign it as a virtual pin in your

Quartus II project.

Table 3–5 describes the files that are associated with the example design and the

testbench.

The example driver is a self-checking test generator for the DDR or DDR2 SDRAM

controller. It uses a state machine to write data patterns to a range of column

addresses, within a range of row addresses in all memory banks. It then reads back

the data from the same locations, and checks that the data matches. The pass not fail

(pnf) output transitions low if any read data fails the comparison. There is also a

pnf_per_byte output, which shows the comparison on a per byte basis. The

test_complete output transitions high for a clock cycle at the end of the write or

read sequence. After this transition the test restarts from the beginning.

The data patterns used are generated using an 8-bit LFSR per byte, with each LFSR

having a different initialization seed.

Figure 3–12. Testbench & Example Design

Example Driver

PLLclock_source

test_complete

pnf

Example Design

Testbench

DDR SDRAM Controller

DDR SDRAM

DIMM Model

Bidrectional Board

Delay Model

DLL

Table 3–5. Example Design & Testbench Files

Filename Description

<project name>_tb.v or .vhd (1) Testbench for the example design.

<project name>.v or .vhd (1) Example design.

ddr_pll_<device family>.v or .vhd (2) Example PLL.

ddr_fb_pll_stratixii.v or .vhd Optional fed-back PLL (Stratix II devices only).

<variation name>_example_driver.v or .vhd Example driver.

<variation name> .v or .vhd Top-level description of the custom MegaCore function.

Notes to Table 3–5:

(1) <project name> is the name of the IP Toolbench-generated example design.

(2) Replace <device family> with stratix for Stratix series, or cyclone for Cyclone series.

1 2 ... 48 49 50 51 52 53 54 55 56 57 58 ... 105 106

Brak uwag

Altera DDR SDRAM Controller Instrukcja Użytkownika Strona 53