Altera DDR SDRAM Controller Instrukcja Użytkownika Strona 93
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A–15
Examples
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
Example A–4 shows the top-level example design file with the resynchronization
clock derived from either the write clock or the system clock.
1 The top-level design does not contain the resync_clk
.
Example A–4. Top-Level Design File (Derived Resynchronization Clock)
ddr2_top ddr2_top_ddr_sdram
(
.clk (clk),
.clk_to_sdram (unused_clk),
.clk_to_sdram_n (unused_clk_n),
.ddr2_a (ddr2_a),
.ddr2_ba (ddr2_ba),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_cke (ddr2_cke),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_dm (ddr2_dm[3 : 0]),
.ddr2_dq (ddr2_dq),
.ddr2_dqs (ddr2_dqs[3 : 0]),
.ddr2_odt (ddr2_odt),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_we_n (ddr2_we_n),
.dqs_delay_ctrl (dqs_delay_ctrl),
.dqsupdate (dqsupdate),
.fedback_clk_out (fedback_clk_out),
.fedback_resynch_clk (fedback_resynch_clk),
.local_addr (ddr2_local_addr),
.local_be (ddr2_local_be),
.local_init_done (),
.local_rdata (ddr2_local_rdata),
.local_rdata_valid (ddr2_local_rdata_valid),
.local_rdvalid_in_n (),
.local_read_req (ddr2_local_read_req),
.local_ready (ddr2_local_ready),
.local_refresh_ack (),
.local_size (ddr2_local_size),
.local_wdata (ddr2_local_wdata),
.local_wdata_req (ddr2_local_wdata_req),
.local_write_req (ddr2_local_write_req),
.postamble_clk (dedicated_postamble_clk),
.reset_n (reset_n),
.stratix_dll_control (stratix_dll_control),
.write_clk (write_clk)
);
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Software Version: 9.0 1
- Document Date: March 2009 1
- UG-DDRSDRAM-10.0 2
- Contents 3
- 1. About This Compiler 5
- Features 6
- General Description 6
- Note to Figure 1–1: 7
- Note to Table 1–3: 8
- Installation and Licensing 9
- OpenCore Plus Evaluation 10
- 2. Getting Started 11
- SOPC Builder Design Flow 12
- Parameterize 14
- Constraints 15
- Add/Update Component 15
- Create Your Top-Level Design 16
- Edit the PLL 17
- Program a Device 18
- Figure 2–1. System Naming 24
- Set Up Simulation 25
- Generate 25
- Simulate the Example Design 27
- Notes to Table 2–2: 29
- Notes to Table 2–3: 30
- Notes to Table 2–4: 31
- Compile the Example Design 32
- Implement Your Design 34
- Set Up Licensing 35
- Control Logic 37
- Datapath 38
- Device-Level Description 41
- Figure 3–3. Datapath Timing 42
- Designing Your Own Controller 43
- DQS Group Block Diagrams 44
- Notes to Figure 3–4: 45
- Notes to Figure 3–5: 46
- Notes to Figure 3–6: 47
- Notes to Figure 3–7: 48
- PLL Configurations 49
- Stratix II Device 50
- Stratix Device 51
- Cyclone II Device 51
- Cyclone Device 51
- DLL Configurations 52
- Example Design 52
- Notes to Table 3–5: 53
- Interface Description 55
- Figure 3–13. Writes 56
- Interfaces & Signals 57
- DDR SDRAM 58
- Interface 58
- Local Interface 58
- [1] [3][2] [5][4] 58
- [1] [2] [3] [4] [6][5] 59
- User Refresh Control 60
- 200 clock cycles 63
- Note to Table 3–7: 65
- Parameters 67
- Controller 69
- Note to Table 3–15: 71
- Controller Timings 73
- Memory Timings 74
- Board Timings 75
- Project Settings 76
- Manual Timings 77
- Simulation Testing 77
- Hardware Testing 77
- (MT46V8M16-75Z) 78
- A. Manual Timing Settings 79
- Resynchronization 82
- Resynchronization Registers 83
- Notes to Figure A–2: 84
- Notes to Figure A–3: 85
- Notes to Figure A–4: 86
- Notes to Table A–5: 87
- Note to Figure A–5: 87
- DQS Postamble 88
- Postamble Logic 89
- System Clock 90
- Postamble 90
- Examples 91
- Board, Cyclone II Edition 95
- D. Maximizing Performance 101
- Adjust the PLL Phases 102
- Assign Pins 102
- Place the Fedback PLL 102
- Update the PLL Phases 103
- Additional Information 105
- Typographic Conventions 106
- Preliminary 106
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