Altera DDR SDRAM Controller Instrukcja Użytkownika Strona 81
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A–3
Parameters
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
Table A–3 shows the capture options (non-DQS mode only).
Postamble clock setting 0 (clk, rising edge),
90 (write_clk, falling
edge),
180 (clk, falling edge)
270 (write_clk, rising
edge), or
dedicated
Selects which clock to use for the postamble logic: the
system clock, the write clock (a 90° advanced version of the
system clock), or a dedicated postamble clock. Also defines
which edge of the chosen clock to use for the postamble
logic. If you select falling edge, the data path automatically
inserts inverters on the clock inputs to the postamble control
registers.
Dedicated clock phase 0 to 359 Allows you to enter the phase of the dedicated postamble
clock that is used for timing analysis. IP Toolbench uses this
value to set up the PLL phase shift.
Number of DQS delay
matching buffers
0 to 8 Inserts the chosen number of delay buffers on the undelayed
DQS in Stratix devices. Insert delay buffers when you are
using low frequencies, to ensure that the capture registers
are not disabled too early.
Table A–2. Postamble Options (Part 2 of 2)
Parameter Range Description
Table A–3. Capture Options
Parameter Range Description
Manual capture control On or off Turn on to specify the details of the clock used for the
capture logic. Otherwise, the details are calculated
automatically based on system timing, “DQS Postamble” on
page A–10.
Capture setting 0 (clk, rising edge),
90 (write_clk, falling
edge),
180 (clk, falling edge)
270 (write_clk, rising
edge), or
dedicated
Selects which clock to use for the capture logic: the system
clock, the write clock (a 90° advanced version of the system
clock), or a dedicated capture clock. Also defines which edge
of the chosen clock to use for the capture logic. If you select
falling edge, the data path automatically inserts inverters on
the clock inputs to the capture registers.
Dedicated clock phase 0 to 359 Allows you to enter the phase of the dedicated capture clock
that is used for timing analysis. IP Toolbench uses this value
to set up the PLL phase shift.
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Software Version: 9.0 1
- Document Date: March 2009 1
- UG-DDRSDRAM-10.0 2
- Contents 3
- 1. About This Compiler 5
- Features 6
- General Description 6
- Note to Figure 1–1: 7
- Note to Table 1–3: 8
- Installation and Licensing 9
- OpenCore Plus Evaluation 10
- 2. Getting Started 11
- SOPC Builder Design Flow 12
- Parameterize 14
- Constraints 15
- Add/Update Component 15
- Create Your Top-Level Design 16
- Edit the PLL 17
- Program a Device 18
- Figure 2–1. System Naming 24
- Set Up Simulation 25
- Generate 25
- Simulate the Example Design 27
- Notes to Table 2–2: 29
- Notes to Table 2–3: 30
- Notes to Table 2–4: 31
- Compile the Example Design 32
- Implement Your Design 34
- Set Up Licensing 35
- Control Logic 37
- Datapath 38
- Device-Level Description 41
- Figure 3–3. Datapath Timing 42
- Designing Your Own Controller 43
- DQS Group Block Diagrams 44
- Notes to Figure 3–4: 45
- Notes to Figure 3–5: 46
- Notes to Figure 3–6: 47
- Notes to Figure 3–7: 48
- PLL Configurations 49
- Stratix II Device 50
- Stratix Device 51
- Cyclone II Device 51
- Cyclone Device 51
- DLL Configurations 52
- Example Design 52
- Notes to Table 3–5: 53
- Interface Description 55
- Figure 3–13. Writes 56
- Interfaces & Signals 57
- DDR SDRAM 58
- Interface 58
- Local Interface 58
- [1] [3][2] [5][4] 58
- [1] [2] [3] [4] [6][5] 59
- User Refresh Control 60
- 200 clock cycles 63
- Note to Table 3–7: 65
- Parameters 67
- Controller 69
- Note to Table 3–15: 71
- Controller Timings 73
- Memory Timings 74
- Board Timings 75
- Project Settings 76
- Manual Timings 77
- Simulation Testing 77
- Hardware Testing 77
- (MT46V8M16-75Z) 78
- A. Manual Timing Settings 79
- Resynchronization 82
- Resynchronization Registers 83
- Notes to Figure A–2: 84
- Notes to Figure A–3: 85
- Notes to Figure A–4: 86
- Notes to Table A–5: 87
- Note to Figure A–5: 87
- DQS Postamble 88
- Postamble Logic 89
- System Clock 90
- Postamble 90
- Examples 91
- Board, Cyclone II Edition 95
- D. Maximizing Performance 101
- Adjust the PLL Phases 102
- Assign Pins 102
- Place the Fedback PLL 102
- Update the PLL Phases 103
- Additional Information 105
- Typographic Conventions 106
- Preliminary 106
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