Altera DDR SDRAM Controller Instrukcja Użytkownika Pobierz pdf (Strona 86)

A–8

Resynchronization

DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Figure A–4 shows the resynchronization registers for Stratix II devices with fed-back

capture (refer to Table 3–15 on page 3–35).

Figure A–4. Resynchronization Registers—Stratix II Devices with Fed-back Capture

Notes to Figure A–4:

(1) IP Toolbench automatically inserts the intermediate resynchronization registers, depending on your choice of resynchronization phase.

(2) IP Toolbench automatically inserts these registers if the design needs them.

clkPLL

Clocked by Capture Clock

local_rdata

resynch_clk

Reclock resynchronized data

to rising edge registers

(see Note 2)

Intermediate resynchronization registers

(see Note 1)

Resynchronization registers

Capture registers

Clocked by Resynchronization Clock

Clocked by System Clock

Fed-back PLL

(Optional)

capture_clk

1 2 ... 81 82 83 84 85 86 87 88 89 90 91 ... 105 106

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