Altera DDR SDRAM Controller Instrukcja Użytkownika Pobierz pdf (Strona 61)

Chapter 3: Functional Description 3–25

Interfaces & Signals

DDR SDRAM Initialization Timing

f DDR SDRAM and DDR2 SDRAM initialization timing is different. For DDR2 SDRAM

initialization timing, refer to “DDR2 SDRAM Initialization Timing” on page 3–26.

The DDR SDRAM controller initializes the SDRAM devices by issuing the following

memory command sequence:

■ NOP (for 200 ms, programmable)

■ PCH

■ Extended LMR (ELMR)

■ LMR

■ NOP (for 200 clock cycles, fixed)

■ PCH

■ ARF

■ LMR

Figure 3–17 on page 3–25 shows a typical initialization timing sequence, which is

described below. The length of time between the reset and the first PCH command

should be 200 ms. This time can be reduced for simulation testing by setting the start-

up timer parameter in IP Toolbench.

1. A PCH command is sent to all banks by setting the precharge pin, the address bit

a[10], or a[8] high.

Figure 3–17. DDR SDRAM Device Initialization Timing

clk

ddr_cke

ddr_a

ddr_ba

ddr_cs_n

ddr_ras_n

ddr_cas_n

ddr_we_n

local_init_done

0 0

0 1 01

0 0 0 0 0 0 00

[1] [2] [3] [4] [6][5][5]

200 clock cycles

Key:

P = PCH

L = LMR

A = ARF

DDR Command P L L P A A LL

1 2 ... 56 57 58 59 60 61 62 63 64 65 66 ... 105 106

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Altera DDR SDRAM Controller Instrukcja Użytkownika Strona 61