Altera JESD204B IP Instrukcja Użytkownika Strona 112
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Figure 5-10: RX Operation Behavior
This figure shows the data transmission for a system configuration of LMF = 112, N = 12, N' = 16, S =1.
Operation:
• Upon the deassertion of the rxframe_rst_n signal, the jesd204_rx_link_data_ready signal from
the deassembler to the DLL is asserted at the next rxframe_clk.
• Subsequently, the DLL asserts the jesd204_rx_link_data_valid signal for the deassembler to
activate the f2_div1_cnt signal logic and to start sampling the jesd204_rx_link_datain[31:0]
signal.
(36)
• At the following rxframe_clk, the jesd204_rx_data_valid is asserted along with the multiplexed
jesd204_rx_dataout[11:0] signal to stream data to the Avalon-ST interface.
• Finally, the DLL deasserts the jesd204_rx_link_data_valid signal when there is no more valid data.
• The deassembler deactivates the f2_div1_cnt signal logic accordingly, and deasserts the
jesd204_rx_data_valid at the next rxframe_clk.
rxframe_clk
rxlink_clk
rxframe_rst_n
rxlink_rst_n
jesd204_rx_link_data_ready
jesd204_rx_link_data_valid
f2_div1_cnt
jesd204_rx_link_datain[31:0]
rxdata_mux_out[15:0]
jesd204_rx_crtlout[0]
jesd204_rx_data_valid
jesd204_rx_data_ready
junk xddcc bbaa
junk
junk
junk
xbbaa ddcc x4433
bbaa
xddcc 4433
xddc xbba xbba xddc x443
xbba
xddc x443
jesd204_rx_dataout[11:0]
junk junk
xddc xbba xbba xddc x443
xbba
xddc x443
RX Data Reception
This section explains when there is a valid RX data out from the DLL to the TL to with scrambler enabled.
The MAC layer process the jesd204_rx_dataout signal once the TL asserts the jesd204_rx_data_valid
signal. However, there are some data that should be discarded by the upper layer when the you enable the
scrambler. This is because the initial unknown seed value within the scrambler can corrupt the very first
eight octets, which is the data for the first two link clock cycles. The data can be translated to the frame
(36)
The f2_div1_cnt signal is internally generated in the RX control block to correctly stream data to the
Avalon-ST interface.
UG-01142
2015.05.04
RX Data Reception
5-31
JESD204B IP Core Design Guidelines
Altera Corporation
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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