Altera JESD204B IP Instrukcja Użytkownika Strona 132
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Figure 5-20: Dynamic Reconfiguration Block Diagram (For 20 nm Device Families—Arria 10)
JESD204B IP Core (Duplex)
CSR PHY
SPI Master
Clock MIF
ROM
DAC MIF
ROM
ADC MIF
ROM
JESD MIF
ROM
Control Unit
PLL MIF
ROM
PLL
Reconfiguration
Avalon-MM Avalon-MM
Avalon-MM
reconfig
runtime_lmf
runtime_datarate
cu_busy
Avalon-MM
PHY MIF
ROM
The MIF ROM content for maximum and downscale configuration:
• PLL MIF ROM—contains the PLL counter, charge pump, and bandwidth setting.
• JESD MIF ROM—contains the LMF information.
• PHY MIF ROM—contains the transceiver channel and PLL setting.
• ADC MIF ROM—contains the ADC converter setting.
• DAC MIF ROM—contains the DAC converter setting.
• CLK MIF ROM—contains the device clock setting.
MIF ROM
You need to generate two MIF files for each reconfigurable IP core as shown in Figure 5-20 or Figure
5-21, and merge them into a single MIF file for each IP core. The following section shows the MIF file
format.
Core PLL
The MIF format is fixed by the PLL. You need to generate two PLLs with maximum and downscale
setting to get these two MIF files. Then, merge the files into one (core_pll.mif). Only the PLL with
maximum configuration is used in final compilation.
Maximum Configuration MIF
WIDTH=32;
DEPTH=92;
ADDRESS_RADIX=UNS;
UG-01142
2015.05.04
MIF ROM
5-51
JESD204B IP Core Design Guidelines
Altera Corporation
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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