Altera JESD204B IP Instrukcja Użytkownika Pobierz pdf (Strona 37)

Testbench Simulation Flow

The JESD204B testbench simulation flow:

1. At the start, the system is under reset (all the components are in reset).

2. After 100 ns, the Transceiver Reset Controller IP core power up and wait for the tx_ready signal from

the Transceiver Reset Controller IP to assert.

3. The reset signal of the JESD204B TX Avalon-MM interface is released (go HIGH) once the tx_ready

signal is asserted. At the next positive edge of the link_clk signal, the JESD204B TX link powers up by

releasing its reset signal.

4. The JESD204B TX link starts transmitting K28.5 characters and wait for the Transceiver Reset

Controller IP core to assert the rx_ready signal.

5. The reset signal of the JESD204B RX Avalon-MM interface is released (go HIGH) once the rx_ready

signal is asserted. At the next positive edge of the link_clk signal, the JESD204B RX link powers up by

releasing its reset signal.

6. Once the link is out of reset, a SYSREF pulse is generated to reset the LMFC counter inside both the

JESD204B TX and RX IP core.

7. When the txlink_ready signal is asserted, the packet generator starts sending packets to the TX

datapath.

8. The packet checker starts comparing the packet sent from the TX datapath and received at the RX

datapath after the rxlink_valid signal is asserted.

9. The testbench reports a pass or fail when all the packets are received and compared.

The testbench concludes by checking that all the packets have been received.

If no error is detected, the testbench issues a TESTBENCH PASSED message stating that the simulation

was successful. If an error is detected, the testbench issues a TESTBENCH FAILED message to indicate

that the testbench has failed.

UG-01142

2015.05.04

Testbench Simulation Flow

3-23

Getting Started

Altera Corporation

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Altera JESD204B IP Instrukcja Użytkownika Strona 37