Altera JESD204B IP Instrukcja Użytkownika Strona 117
- Strona / 158
- Spis treści
- BOOKMARKI
Oceniono. / 5. Na podstawie oceny klientów
RX Latency
The RX latency is defined as the time needed to fully transfer a 32-bit data in a lane
(jesd204_rx_link_datain*) to the Avalon-ST interface (jesd204_rx_dataout*) when the
jesd204_rx_link_data_valid signal equals to "1".
Table 5-17: RX Latency Associated with Different F and FRAMECLK_DIV Settings.
F FRAMECLK_DIV RX Latency
1 1
• Maximum 5 rxframe_clk period for byte 3
• Minimum 2 rxframe_clk period for byte 0
1 4 2 rxframe_clk period
2 1
• Maximum 3 rxframe_clk period for byte 2 and byte 3
• Minimum 2 rxframe_clk period for byte 0 and byte 1
2 2 2 txframe_clk period
4 — 2 txframe_clk period
8 — 2 txframe_clk period
Serial Port Interface (SPI)
An external converter device with a SPI allows you to configure the converter for specific functions or
operations through a structured register space provided inside the converter device. The SPI gives
flexibility and customization, depending on the application. Addresses are accessed via the serial port and
can be written to or read from the port. The memory is organized into bytes that can be further divided
into fields.
The SPI communicates using two data lines, a control line, and a synchronization clock. A single SPI
master can work with multiple slaves. The SPI core logic is synchronous to the clock input provided by
the Avalon-MM interface. When configured as a master, the core divides the Avalon-MM clock to
generate the SCLK output.
Figure 5-13: Serial Port Interface (24-bit) Timing Diagram
Figure shows the timing diagram of a 24-bit SPI transaction required by a typical external converter
device.
R/W
W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0Don’t Care
Don’t Care Don’t Care
Don’t Care
SS_n
SCLK
SDIO
The first 16 bits are instruction data. The first bit in the stream is the read or write indicator bit. This bit
goes high to indicate a read request. W1 and W0 represent the number of data bytes to transfer for either
a read or write process. For implementation simplicity, W1 and W0 are always set at 0 in this design
5-36
RX Latency
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Design Guidelines
Send Feedback
- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera JESD204B IP
Urządzenia pomiarowe Altera Nios II Embedded Evaluation Kit Cyclone III Editio Instrukcja Użytkownika
(80 strony)
(80 strony)
Urządzenia pomiarowe Altera Phase-Locked Loop Reconfiguration IP Core Instrukcja Użytkownika
(51 strony)
(51 strony)
Urządzenia pomiarowe Altera Serial Digital Interface (SDI) MegaCore Function Instrukcja Użytkownika
(140 strony)
(140 strony)
Urządzenia pomiarowe Altera 100G Development Kit, Stratix V GX Edition Instrukcja Użytkownika
(44 strony)
(44 strony)
Urządzenia pomiarowe Altera Stratix V Avalon-MM Interface for PCIe Solutions Instrukcja Użytkownika
(184 strony)
(184 strony)
Urządzenia pomiarowe Altera 10-Gbps Ethernet MAC MegaCore Function Instrukcja Użytkownika
(175 strony)
(175 strony)
© 2020, manymanuals.pl. Wszelkie prawa zastrzeżone. | 0.115 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentarze do niniejszej Instrukcji