Altera Low Latency Ethernet 10G MAC Instrukcja Użytkownika Strona 6
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Features
The LL Ethernet 10G MAC supports the following features:
• Full-duplex MAC in four operating modes: 10G, 1G/10G, or 10M/100M/1G/10G).
• Three variations for selected operating modes: MAC Tx only block, MAC Rx only block, and MAC Tx
and MAC Rx block.
• Interfaces:
• Client-side—32-bit Avalon-ST interface.
• PHY-side—32-bit XGMII, 16-bit GMII, or 4-bit MII depending on the operating mode.
• Management—32-bit Avalon-MM interface.
• Virtual local area network (VLAN) and stacked VLAN tagged frames decoding (type 'h8100).
• Cyclic redundancy code (CRC)-32 computation and insertion on the TX datapath. Optional CRC
checking and forwarding on the RX datapath.
• Deficit idle counter (DIC) for optimized performance with average inter-packet gap (IPG) for LAN
applications.
• Optional statistics collection on TX and RX datapaths.
• Programmable maximum length of TX and RX data frames up to 64 Kbytes (KB).
• Programmable promiscuous (transparent) mode.
• Optional padding insertion on the TX datapath and termination on the RX datapath.
• Ethernet flow control using pause frames.
• Optional timestamping feature as specified by IEEE 1588v2 for the following configurations:
• 10GbE MAC with 10GBASE-R PHY IP core
• 1G/10GbE MAC with 1G/10GbE PHY IP core
• 10M/100M/1G/10GbE MAC with 10M-10GbE PHY IP core
• Optional features for 10G operating mode:
• Unidirectional feature as specified by IEEE 802.3 (Clause 66).
• Priority-based flow control (PFC) with programmable pause quanta. PFC supports 2 to 8 priority
queues.
• Preamble passthrough mode on TX and RX datapaths, which allows user-defined preamble in the
client frame. This feature is supported only in the 10G operating mode.
• 10GBASE-R register mode on the TX and RX datapaths, which enables lower latency.
1-2
Features
UG-01144
2014.12.15
Altera Corporation
About LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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