Altera Low Latency Ethernet 10G MAC Instrukcja Użytkownika Strona 3
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Oceniono. / 5. Na podstawie oceny klientów
Length Checking............................................................................................................................3-14
CRC and Padding Bytes Removal................................................................................................3-15
Overflow Handling........................................................................................................................3-16
RX Timing Diagrams.................................................................................................................... 3-16
Flow Control...............................................................................................................................................3-17
IEEE 802.3 Flow Control.............................................................................................................. 3-17
Priority-Based Flow Control........................................................................................................ 3-19
Reset Requirements................................................................................................................................... 3-20
Supported PHYs.........................................................................................................................................3-21
10GBASE-R Register Mode..........................................................................................................3-22
XGMII Error Handling (Link Fault).......................................................................................................3-23
IEEE 1588v2................................................................................................................................................3-25
Architecture....................................................................................................................................3-25
Transmit Datapath.........................................................................................................................3-26
Receive Datapath............................................................................................................................3-27
Frame Format.................................................................................................................................3-27
Configuration Registers for LL Ethernet 10G MAC.......................................... 4-1
Register Map.................................................................................................................................................4-1
Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers..................4-2
Register Access............................................................................................................................................. 4-4
Primary MAC Address................................................................................................................................4-5
MAC Reset Control Register......................................................................................................................4-5
TX_Configuration and Status Registers................................................................................................... 4-6
Flow Control Registers..............................................................................................................................4-10
Unidirectional Control Registers.............................................................................................................4-12
RX Configuration and Status Registers.................................................................................................. 4-13
TX Timestamp Registers...........................................................................................................................4-18
Calculating TX Timing Adjustments..........................................................................................4-20
RX Timestamp Registers...........................................................................................................................4-21
Calculating RX Timing Adjustments..........................................................................................4-23
ECC Registers.............................................................................................................................................4-24
Statistics Registers......................................................................................................................................4-25
Interface Signals for LL Ethernet 10G MAC.......................................................5-1
Clock and Reset Signals...............................................................................................................................5-1
Speed Selection Signal................................................................................................................................. 5-3
Error Correction Signals.............................................................................................................................5-3
Unidirectional Signals.................................................................................................................................5-4
Avalon-MM Programming Signals...........................................................................................................5-4
Avalon-ST Data Interfaces..........................................................................................................................5-5
Avalon-ST TX Data Interface Signals........................................................................................... 5-5
Avalon-ST RX Data Interface Signals........................................................................................... 5-6
Avalon-ST Flow Control Signals............................................................................................................... 5-7
Avalon-ST Status Interface.........................................................................................................................5-8
Avalon-ST TX Status Signals..........................................................................................................5-8
Avalon-ST RX Status Signals........................................................................................................5-10
Low Latency Ethernet 10G MAC User Guide
TOC-3
Altera Corporation
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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