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Overflow Handling
When an overflow occurs on the client side, the client can backpressure the Avalon-ST receive interface
by deasserting the avalon_st_rx_ready signal. If an overflow occurs in the middle of frame transmission,
the MAC RX truncates the frame by sending out the avalon_st_rx_endofpacket signal after the
avalon_st_rx_ready signal is reasserted. The error bit, avalon_st_rx_error[5], is set to 1 to indicate
an overflow. If there is an overflow during client data reception, the current frame will get truncated. The
MAC RX will drop the remaining payload of the erroneous frame and the subsequent frames if the
overflow condition persists. The MAC RX then continues to receive data when the overflow condition
ceases.
RX Timing Diagrams
Figure 3-15: Back-to-back Transmission of Normal Frames with CRC Removal Enabled
The following diagram shows back-to-back reception of normal frames with CRC removal enabled.
rx_312_5_clk
xgmii_rx_data[31:0]
xgmii_rx_control[3:0]
avalon_st_rx_startofpacket
avalon_st_rx_valid
avalon_st_rx_ready
avalon_st_trx_endofpacket
avalon_st_rx_data[31:0]
avalon_st_rx_empty[1:0]
avalon_st_rx_error[5:0]
avalon_st_rx_data[31:24]
avalon_st_rx_data[23:16]
avalon_st_rx_data[15:8]
avalon_st_rx_data[7:0]
xgmii_rx_data[7:0]
xgmii_rx_data[15:8]
xgmii_rx_data[23:16]
xgmii_rx_data[31:24]
* *fff * * * * *c 0000_0000 *
0faa_4s5e
* * * * * * * * * *
1 0 1f 0 1f 0
* *fff *0 * *
0707_0707
* *0 0000_0000 * * * *
fb *ff cf 88 21 22 8cc 00 fd
07
fb 3a 00 c0 0a 4d da * cd3a b6 fa 07
01 81
87 95 46 94 f2
88 ff 58 08 d3 be 88 00 07
07
88 3a 01 16 51 ae c5 * 403a df 55
80 00
f3 c7 46 df f6
88 d0 d5 cd a7 ff 00 07
07
88 3a 0a 50 51 2e 2b * 0a3a 62 73
c2
46 97 24 43 aa
88 ad 49 f5 2a 00 07
07
88 d5 d9 6d 18 8d 57 * 7cd5 2b f1
00
3e 28 55 70 95
ff 61
68 03
5c 81ff 60
fb ff 88
b6
07
22 8c 00 07 3a 01 c0
3a cf f121
00fb
88 ff 08
df
07
be 89 00 07 3a 80 16
3a 58 55d3
0188
88 d5
62
07
a7 ff 00 07 3a c2 50
3a d0 73cd
0a88
ff 61
88 49
2b
07
2a 00 07 d5 00 6d
d5 ad f1f5
d988
ff 60
3-16
Overflow Handling
UG-01144
2014.12.15
Altera Corporation
Functional Description of LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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