Altera Low Latency Ethernet 10G MAC Instrukcja Użytkownika Strona 73
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Oceniono. / 5. Na podstawie oceny klientów
Step Description 10G 10M, 100M or 1G
2 Convert the digital
latency in UI to ns.
123 UI * 0.097 = 11.931 ns 53 UI * 0.8 = 42.4 ns
3 Add the analog latency
to the digital latency in
ns.
11.931 ns + (-1.1 ns) = 10.831 ns 42.4 ns + (-1.1 ns) = 41.3 ns
4 Add any external PHY
delay to the total
obtained in step 3. In
this example, an
external PHY delay of
1 ns is assumed.
10.831 ns + 1 ns = 11.831 ns 41.3 ns + 1 ns = 42.3 ns
5 Convert the total
latency to ns and fns
in hexadecimal.
ns: 0xB
fns: 0.831 * 65536 = 0xD4BC
ns: 0x17
fns: 0.3 * 65536 = 0x4CCC
6 Configure the
respective registers.
tx_ns_adjustment_10G = 0xB
tx_fns_adjustment_10G = 0xD4BC
tx_ns_adjustment_mult_speed =
0x17
tx_fns_adjustment_mult_speed
= 0x4CCC
The Quartus II simulation model is cycle accurate for the PCS, but not for the PMA. The latency values
reported are therefore different from the hardware.
Table 4-13: PMA Delay from Simulation Model
Delay Device
PMA Mode
(bit)
Timing Adjustment
MAC Configurations
TX Register RX Register
Digita
l
Arria V GZ and
Stratix V
40 41 UI 150.5 UI 10GbE or 10G of 10M-10GbE
32 33 UI 196 UI 10GbE
10 11 UI 33.5 UI 1G/100M/10M of 10M-10GbE
Arria 10
40 151.5 UI 65.5 UI 10GbE or 10G of 10M-10GbE
10 32 UI 23.5 UI 1G/100M/10M of 10M-10GbE
RX Timestamp Registers
The RX timestamp registers are used when you turn on Enable time stamping. They are reserved when
not used.
UG-01144
2014.12.15
RX Timestamp Registers
4-21
Configuration Registers for LL Ethernet 10G MAC
Altera Corporation
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- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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