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In this example, the latency of the multiplier is set to five clock cycles, while none is being set for the
absolute value function. Thus, the absolute value result only appears at the result[] port five cycles after
the input values are captured on the input ports.
The dataa[] and datab[] values in the simulation waveform above portray the two input values that are
being fed to the multiplier. The value in the result[] port depicts the multiplication result that has gone
through the absolute value operation.
This table lists the inputs and corresponding outputs obtained from the simulation.
Table 15-2: Summary of Input Values and Corresponding Outputs
Time Event
0 ns, start-up dataa[] value: C080 0000h
datab[] value: 4000 0000h
Output value: All values seen on the output port before the 5th clock cycle are
merely due to the behavior of the system during start-up and should be
disregarded.
22.5 ns Output value: 4100 0000h
The multiplication of a negative number with a positive number results in a
negative number. The absolute value of the result is reflected on the result[]
port.
20 ns dataa[] value: 579D F479h
datab[] value: 7F80 0000h
The value of dataa[] is normal while the value of datab[] is infinity.
42.5 ns Output value: 7F80 0000h
Exception handling ports: overflow asserts
The multiplication of a normal value with infinity results in infinity and sets
the overflow port in the multiplier. The absolute value of the output is infinity
and the overflow port is also set as this assertion of the port is being carried
through from the corresponding overflow port in the multiplier.
ALTFP_ABS Signals
UG-01058
2014.12.19
ALTFP_ABS Signals
15-3
ALTFP_ABS IP Core
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About Floating-Point IP Cores 7
- Design Flow 8
- Using the Parameter Editor 10
- File Name Description 12
- Upgrading IP Cores 15
- Related Information 18
- Floating-Point Formats 19
- Special Case Numbers 20
- Non-IEEE-754 Standard Format 21
- Integer bits 22
- Fraction bits 22
- VHDL Component Declaration 24
- VHDL LIBRARY-USE Declaration 24
- ALTERA_FP_MATRIX_INV IP Core 25
- Triangular Matrix Inversion 29
- Matrix Multiplication 29
- Matrix Inversion Operation 29
- Precision Format Numbers 30
- Sample Matrix Data 32
- Matrix Data 33
- ALTERA_FP_MATRIX_INV Signals 34
- ALTERA_FP_MATRIX_MULT IP Core 36
- . . . N-10 . . 38
- . . . N-10 38
- ALTERA_FP_MATRIX_MULT 39
- Parameter Value Description 40
- ALTERA_FP_ACC_CUSTOM IP Core 42
- ALTERA_FP_ACC_CUSTOM Signals 44
- ALTFP_ADD_SUB IP Core 48
- ALTFP_ADD_SUB Signals 51
- ALTFP_ADD_SUB 52
- ALTFP_ADD_SUB Parameters 53
- ALTFP_DIV IP Core 55
- ALTFP_DIV Truth Table 56
- ALTFP_DIV Signals 60
- ALTFP_DIV Parameters 61
- ALTFP_MULT IP Core 63
- Parameters 66
- ALTFP_MULT Signals 67
- ALTFP_SQRT 69
- ALTFP_SQRT Truth Table 70
- ALTFP_SQRT Signals 72
- ALTFP_SQRT Parameters 74
- ALTFP_EXP IP Core 75
- ALTFP_EXP Signals 78
- ALTFP_EXP 79
- ALTFP_EXP Parameters 80
- ALTFP_INV IP Core 81
- ALTFP_INV_SQRT IP Core 87
- ALTFP_INV_SQRT 90
- ALTFP_LOG 93
- ALTFP_ATAN IP Core 99
- ALTFP_ATAN Parameters 100
- Parameter 101
- Type Required Description 101
- ALTFP_SINCOS IP Core 102
- ALTFP_SINCOS Signals 103
- ALTFP_SINCOS Parameters 104
- ALTFP_ABS IP Core 105
- UG-01058 106
- 2014.12.19 106
- ALTFP_ABS Signals 107
- ALTFP_ABS 108
- ALTFP_ABS Parameters 109
- ALTFP_COMPARE IP Core 111
- Format Numbers 112
- ALTFP_COMPARE Signals 113
- ALTFP_COMPARE Parameters 114
- ALTFP_CONVERT IP Core 116
- ALTFP_CONVERT Output Latency 117
- Point Format Numbers 121
- Time Event 122
- ALTFP_CONVERT Signals 123
- ALTFP_CONVERT Parameters 125
- ALTERA_FP_FUNCTIONS IP Core 128
- Function Description 129
- ALTERA_FP_FUNCTIONS Signals 151
- Altera Corporation 152
- Send Feedback 152
- Document Revision History 156
- Date Document 157
- Changes Made 157
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