Altera Floating-Point Instrukcja Użytkownika Strona 2
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Contents
About Floating-Point IP Cores...........................................................................1-1
List of Floating-Point IP Cores.................................................................................................................. 1-1
Installing and Licensing IP Cores..............................................................................................................1-2
Design Flow.................................................................................................................................................. 1-2
IP Catalog and Parameter Editor...................................................................................................1-3
Specifying IP Core Parameters and Options................................................................................1-4
Specifying IP Core Parameters and Options (Legacy Parameter Editors)...............................1-8
Upgrading IP Cores.....................................................................................................................................1-9
Migrating IP Cores to a Different Device...................................................................................1-12
Floating-Point IP Cores General Features..............................................................................................1-12
IEEE-754 Standard for Floating-Point Arithmetic............................................................................... 1-13
Floating-Point Formats.................................................................................................................1-13
Special Case Numbers...................................................................................................................1-14
Rounding.........................................................................................................................................1-15
Non-IEEE-754 Standard Format.............................................................................................................1-15
Floating-Points IP Cores Output Latency..............................................................................................1-16
Floating-Point IP Cores Design Example Files......................................................................................1-16
VHDL Component Declaration.............................................................................................................. 1-18
VHDL LIBRARY-USE Declaration.........................................................................................................1-18
ALTERA_FP_MATRIX_INV IP Core................................................................2-1
ALTERA_FP_MATRIX_INV Features....................................................................................................2-1
ALTERA_FP_MATRIX_INV Output Latency....................................................................................... 2-1
ALTERA_FP_MATRIX_INV Resource Utilization and Performance................................................2-1
ALTERA_FP_MATRIX_INV Functional Description..........................................................................2-2
Cholesky Decomposition Function...............................................................................................2-3
Triangular Matrix Inversion...........................................................................................................2-5
Matrix Multiplication......................................................................................................................2-5
Matrix Inversion Operation........................................................................................................... 2-5
ALTERA_FP_MATRIX_INV Design Example: Matrix Inverse of Single-Precision Format
Numbers.................................................................................................................................................. 2-6
ALTERA_FP_MATRIX_INV Design Example: Understanding the Simulation Results..... 2-7
Sample Matrix Data.....................................................................................................................................2-8
ALTERA_FP_MATRIX_INV Signals.....................................................................................................2-10
ALTERA_FP_MATRIX_INV Parameters.............................................................................................2-11
ALTERA_FP_MATRIX_MULT IP Core............................................................3-1
ALTERA_FP_MATRIX_MULT Features................................................................................................3-1
ALTERA_FP_MATRIX_MULT Output Latency...................................................................................3-1
ALTERA_FP_MATRIX_MULT Resource Utilization and Performance........................................... 3-1
ALTERA_FP_MATRIX_MULT Functional Description......................................................................3-2
TOC-2
Altera Corporation
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About Floating-Point IP Cores 7
- Design Flow 8
- Using the Parameter Editor 10
- File Name Description 12
- Upgrading IP Cores 15
- Related Information 18
- Floating-Point Formats 19
- Special Case Numbers 20
- Non-IEEE-754 Standard Format 21
- Integer bits 22
- Fraction bits 22
- VHDL Component Declaration 24
- VHDL LIBRARY-USE Declaration 24
- ALTERA_FP_MATRIX_INV IP Core 25
- Triangular Matrix Inversion 29
- Matrix Multiplication 29
- Matrix Inversion Operation 29
- Precision Format Numbers 30
- Sample Matrix Data 32
- Matrix Data 33
- ALTERA_FP_MATRIX_INV Signals 34
- ALTERA_FP_MATRIX_MULT IP Core 36
- . . . N-10 . . 38
- . . . N-10 38
- ALTERA_FP_MATRIX_MULT 39
- Parameter Value Description 40
- ALTERA_FP_ACC_CUSTOM IP Core 42
- ALTERA_FP_ACC_CUSTOM Signals 44
- ALTFP_ADD_SUB IP Core 48
- ALTFP_ADD_SUB Signals 51
- ALTFP_ADD_SUB 52
- ALTFP_ADD_SUB Parameters 53
- ALTFP_DIV IP Core 55
- ALTFP_DIV Truth Table 56
- ALTFP_DIV Signals 60
- ALTFP_DIV Parameters 61
- ALTFP_MULT IP Core 63
- Parameters 66
- ALTFP_MULT Signals 67
- ALTFP_SQRT 69
- ALTFP_SQRT Truth Table 70
- ALTFP_SQRT Signals 72
- ALTFP_SQRT Parameters 74
- ALTFP_EXP IP Core 75
- ALTFP_EXP Signals 78
- ALTFP_EXP 79
- ALTFP_EXP Parameters 80
- ALTFP_INV IP Core 81
- ALTFP_INV_SQRT IP Core 87
- ALTFP_INV_SQRT 90
- ALTFP_LOG 93
- ALTFP_ATAN IP Core 99
- ALTFP_ATAN Parameters 100
- Parameter 101
- Type Required Description 101
- ALTFP_SINCOS IP Core 102
- ALTFP_SINCOS Signals 103
- ALTFP_SINCOS Parameters 104
- ALTFP_ABS IP Core 105
- UG-01058 106
- 2014.12.19 106
- ALTFP_ABS Signals 107
- ALTFP_ABS 108
- ALTFP_ABS Parameters 109
- ALTFP_COMPARE IP Core 111
- Format Numbers 112
- ALTFP_COMPARE Signals 113
- ALTFP_COMPARE Parameters 114
- ALTFP_CONVERT IP Core 116
- ALTFP_CONVERT Output Latency 117
- Point Format Numbers 121
- Time Event 122
- ALTFP_CONVERT Signals 123
- ALTFP_CONVERT Parameters 125
- ALTERA_FP_FUNCTIONS IP Core 128
- Function Description 129
- ALTERA_FP_FUNCTIONS Signals 151
- Altera Corporation 152
- Send Feedback 152
- Document Revision History 156
- Date Document 157
- Changes Made 157
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