Altera V-Series Avalon-MM DMA Instrukcja Użytkownika Strona 50
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Signal Direction Description
• 00110: config.Linkwidthstart
• 00111: Config.Linkaccept
• 01000: Config.Lanenumaccept
• 01001: Config.Lanenumwait
• 01010: Config.Complete
• 01011: Config.Idle
• 01100: Recovery.Rcvlock
• 01101: Recovery.Rcvconfig
• 01110: Recovery.Idle
• 01111: L0
• 10000: Disable
• 10001: Loopback.Entry
• 10010: Loopback.Active
• 10011: Loopback.Exit
• 10100: Hot.Reset
• 10101: L0s
• 11001: L2.transmit.Wake
• 11010: Speed.Recovery
• 11011: Recovery.Equalization, Phase 0
• 11100: Recovery.Equalization, Phase 1
• 11101: Recovery.Equalization, Phase 2
• 11110: recovery.Equalization, Phase 3
rx_par_err
Output When asserted for a single cycle, indicates that a parity error was
detected in a TLP at the input of the RX buffer. This error is
logged as an uncorrectable internal error in the VSEC registers.
For more information, refer to Uncorrectable Internal Error
Status Register. You must reset the Hard IP if this error occurs
because parity errors can leave the Hard IP in an unknown state.
The signal is not available for Arria V and Cyclone V devices.
tx_par_err[1:0]
Output When asserted for a single cycle, indicates a parity error during
TX TLP transmission. These errors are logged in the VSEC
register. The following encodings are defined:
• 2’b10: A parity error was detected by the TX Transaction
Layer. The TLP is nullified and logged as an uncorrectable
internal error in the VSEC registers. For more information,
refer to Uncorrectable Internal Error Status Register.
• 2’b01: Some time later, the parity error is detected by the TX
Data Link Layer which drives 2’b01 to indicate the error.
Reset the IP core when this error is detected. Contact Altera
technical support if resetting becomes unworkable.
UG-01154
2014.12.18
Reset, Status, and Link Training Signals
4-19
Interfaces and Signal Descriptions
Altera Corporation
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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