Altera V-Series Avalon-MM DMA Instrukcja Użytkownika Strona 3
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Table 1-1: PCI Express Data Throughput
The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 2, 4, and 8
lanes. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2, and
8.0 giga-transfers per second for Gen3. This table provides bandwidths for a single transmit (TX) or receive (RX)
channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20%
overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding to less
than 1%.
Link Width in Gigabits Per Second (Gbps)
×2 ×4 ×8
PCI Express Gen1 (2.5 Gbps)
N/A N/A
16
PCI Express Gen2 (5.0 Gbps) 8 16 32
PCI Express Gen3 (8.0 Gbps) 15.75 31.51 63
Related Information
• PCI Express Base Specification 2.1 or 3.0
• PCI Express DMA Reference Design for Stratix V Devices
• Creating a System with Qsys
Features
New features in the Quartus
®
II 14.1 software release:
• New PCI Express Multi-Channel DMA Interface IP Core to demonstrate multi-channel operation.
This component is available in the Qsys IP Catalog under Interface Protocols > PCI Express > Qsys
Example Designs
• New Avalon-MM DMA FIFO Mode IP Core for PCI Express to provide a FIFO interface to the Data
Mover included in the Avalon-MM bridge. This component is available in the Qsys IP Catalog under
Interface Protocols > PCI Express > Qsys Example Designs
• Support for 128-Bit Avalon-MM RX master.
• Reduced Quartus II compilation warnings by 50%.
The V-Series Avalon-MM DMA for PCI Express supports the following features:
• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as
hard IP.
• Native support for Gen1 x8, Gen2 x4, Gen2 x8, Gen3 x4, Gen3 x8 for Endpoints. The variant
downtrains when plugged into a lesser link width or changes to a different maximum link rate.
• Dedicated 16 KByte receive buffer.
• Optional hard reset controller for Gen2.
• Support for 128- or 256-bit Avalon-MM interface to Application Layer with embedded DMA up to
Gen3 ×8 data rate.
• Support for 32- or 64-bit addressing for the Avalon-MM interface to the Application Layer.
• Qsys example designs demonstrating parameterization, design modules, and connectivity.
1-2
Features
UG-01154
2014.12.18
Altera Corporation
Datasheet
Send Feedback
- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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