Altera V-Series Avalon-MM DMA Instrukcja Użytkownika Strona 18
- Strona / 142
- Spis treści
- BOOKMARKI
Oceniono. / 5. Na podstawie oceny klientów
Parameter Value
Path
<working_dir>//pcie_de_ep_dma_g3x8_integrated
6. Click Generate.
Qsys generates the testbench.
Understanding the Simulation Generated Files
Table 2-2: Qsys Generation Output Files
Directory Description
<testbench_dir>/<variant_name>/testbench
Includes testbench subdirectories for the Aldec,
Cadence, Mentor, and Synopsys simulation tools
with the required libraries and simulation scripts.
<testbench_dir>/<variant_name>/testbench/<cad_
vendor>
Includes the HDL source files and scripts for the
simulation testbench.
<testbench_dir>/<variant_name>/testbench/<variant_
namer>_tb
Includes HDL design files
Understanding Simulation Log File Generation
Starting with the Quartus II 14.0 software release, simulation automatically creates a log file, altpcie_
monitor_<dev>_dlhip_tlp_file_log.log in your simulation directory.
Table 2-3: Sample Simulation Log File Entries
Time TLP Type Payload
(Bytes)
TLP Header
17989 RX CfgRd0 0004 04000001_0000000F_01080008
17989 RX MRd 0000 00000000_00000000_01080000
18021 RX CfgRd0 0004 04000001_0000010F_0108002C
18053 RX CfgRd0 0004 04000001_0000030F_0108003C
18085 RX MRd 0000 00000000_00000000_0108000C
Simulating the Example Design in ModelSim
1. In a terminal window, change directory to <workingdir>/pcie_de_ep_dma_g3x8_integrated/testbench/
mentor/ .
2. Start the ModelSim
®
simulator.
3. To run the simulation, type the following commands in a terminal window:
a. do msim_setup.tcl
b. ld_debug
2-4
Understanding the Simulation Generated Files
UG-01154
2014.12.18
Altera Corporation
Getting Started with the Avalon-MM DMA
Send Feedback
- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera V-Series Avalon-MM DMA
Urządzenia pomiarowe Altera 100G Development Kit, Stratix V GX Edition Instrukcja Użytkownika
(76 strony)
(76 strony)
Urządzenia pomiarowe Altera Arria II GX FPGA Development Board, 6G Edition Instrukcja Użytkownika
(62 strony)
(62 strony)
Urządzenia pomiarowe Altera Cyclone IV GX Transceiver Starter Board Instrukcja Użytkownika
(40 strony)
(40 strony)
Urządzenia pomiarowe Altera DSP Development Kit, Stratix V Edition Instrukcja Użytkownika
(74 strony)
(74 strony)
Urządzenia pomiarowe Altera Transceiver Signal Integrity Development Kit, Stra Instrukcja Użytkownika
(42 strony)
(42 strony)
© 2020, manymanuals.pl. Wszelkie prawa zastrzeżone. | 0.154 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentarze do niniejszej Instrukcji