Altera V-Series Avalon-MM DMA Instrukcja Użytkownika Strona 42
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Bits Name Description
[153:14
6]
DMA Descriptor ID
Specifies up to 128 descriptors.
[159:15
4]
Reserved
—
DMA Descriptor Status Bus when Instantiated Separately
Read DMA and Write DMA modules report status to the Descriptor Controller on the RdDmaTx-
Data_o[31:0] or WrDmaTxData_o[31:0] bus when one of the following trigger events occurs:
• A descriptor is activated
• A descriptor completes successfully
The following table shows the mappings of the triggering events to the DMA descriptor status bus:
Table 4-11: DMA Status Bus
Bits Name Description
[31:9] Reserved. —
[8]
Done
When asserted, a single DMA descriptor has completed success‐
fully.
[7:0] Descriptor ID The ID of the descriptor whose status is being reported.
Descriptor Controller Interfaces when Instantiated Internally
Read Descriptor Controller Avalon-MM Master Port
The Read Descriptor Controller Avalon-MM master port drives the TX Avalon-MM slave port. This port
drives single dword transactions to the V-Series Avalon-MM DMA for PCIe. The Read Descriptor
Controller uses this port to write descriptor status to the PCIe domain and possibly to MSI when MSI
messages are enabled.
Table 4-12: Read Descriptor Controller Avalon-MM Master Interface
Signal Name Direction Description
RdDCMAddress_o[63:0]
Output Specifies the address for the read data.
RdDCMByteEnable_
o[3:0]
Output Specifies which data bytes are valid.
RdDCMReadDataValid_i
Input When asserted, indicates that the read data is valid.
RdDCMReadData_o[31:0]
Output
Drives the single dword read data.
UG-01154
2014.12.18
DMA Descriptor Status Bus when Instantiated Separately
4-11
Interfaces and Signal Descriptions
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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