Altera V-Series Avalon-MM DMA Instrukcja Użytkownika Strona 139
- Strona / 142
- Spis treści
- BOOKMARKI
Oceniono. / 5. Na podstawie oceny klientów
Date Version Changes Made
• Corrected the name of the Descriptor Instructions bus. The letters
DMA are now Ast. For example WrDMARXValid_i is now
WrAstRXValid_i.
• Added RD_CONTROL and WR_CONTROL register Done bit. When set,
the Descriptor Controller writes this bit for each descriptor in the
status table and sends a single MSI interrupt after the final
descriptor completes.
• Removed the following chapters that have minimal relevance to
the V-Series Avalon-MM DMA Interface IP Core. These chapters
are available in the more comprehensive Avalon-ST versions :
• Design Implementation
• Optional Features
• Debugging
• Throughput Optimization
2013.12.02 13.1 Arria 10
Initial release.
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the following table.
Contact
(1)
Contact Method Address
Technical support Website www.altera.com/support
Technical training
Website www.altera.com/training
Email [email protected]
Product literature Website www.altera.com/literature
Note to Table:
1. You can also contact your local Altera sales office or sales representative.
Related Information
• Technical Support
• Technical Training
• Customer Training
B-4
How to Contact Altera
UG-01154
2014.12.18
Altera Corporation
Additional Information
Send Feedback
- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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