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Table 4-23: PIPE Interface Signals
In the following table, signals that include lane number 0 also exist for lanes 1-7. These signals are for simulation
only. For Quartus II software compilation, these pipe signals can be left floating. In Qsys, the signals that are part
of the PIPE interface have the prefix, hip_pipe. The signals which are included to simulate the PIPE interface have
the prefix, hip_pipe_sim_pipe
Signal Direction Description
eidleinfersel0[2:0]
Output Electrical idle entry inference mechanism selection. The
following encodings are defined:
• 3'b0xx: Electrical Idle Inference not required in current
LTSSM state
• 3'b100: Absence of COM/SKP Ordered Set the in 128 us
window for Gen1 or Gen2
• 3'b101: Absence of TS1/TS2 Ordered Set in a 1280 UI interval
for Gen1 or Gen2
• 3'b110: Absence of Electrical Idle Exit in 2000 UI interval for
Gen1 and 16000 UI interval for Gen2
• 3'b111: Absence of Electrical idle exit in 128 us window for
Gen1
phystatus0
Input PHY status <n>. This signal communicates completion of several
PHY requests.
powerdown0[1:0] Output Power down <n>. This signal requests the PHY to change its
power state to the specified state (P0, P0s, P1, or P2).
rxdata0[31:0] Input Receive data. This bus receives data on lane <n>.
rxdatak0[3:0]
Input Data/Control bits for the symbols of receive data. Bit 0
corresponds to the lowest-order byte of rxdata, and so on. A
value of 0 indicates a data byte. A value of 1 indicates a control
byte. For Gen1 and Gen2 only.
rxelecidle0 Input Receive electrical idle <n>. When asserted, indicates detection of
an electrical idle.
rxpolarity0 Output Receive polarity <n>. This signal instructs the PHY layer to
invert the polarity of the 8B/10B receiver decoding block.
rxstatus0[2:0] Input Receive status <n>. This signal encodes receive status and error
codes for the receive data stream and receiver detection.
rxvalid0 Input Receive valid <n>. This symbol indicates symbol lock and valid
data on rxdata<n> and rxdatak <n>.
4-34
PIPE Interface Signals
UG-01154
2014.12.18
Altera Corporation
Interfaces and Signal Descriptions
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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