Altera POS-PHY Level 4 IP Core Instrukcja Użytkownika Strona 4
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1–2 Chapter 1: About This IP Core
Features
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
Table 1–3 shows the level of support offered by the POS-PHY Level 4 IP core to each
Altera device family.
Features
■ Compliant with all applicable standards, including:
■ Optical Internetworking Forum (OIF), System Packet Interface Level 4 (SPI-4)
Phase 2 Revision 1: OC-192 System Interface for Physical and Link Layer Devices,
OIF-SPI4-02.1, October 2003.
■ PMC-Sierra Inc., POS-PHY
TM
Level 4 A Saturn Packet and Cell Interface
Specification for OC-192 SONET/SDH and 10 GB/s Ethernet Applications, Issue 5
(Draft): June 2000.
■ Stratix III, Stratix IV, and Stratix V device support up to 1,250 Mbps and Stratix II
device support up to 1,040 Mbps, including integrated dynamic phase alignment
(DPA) hardware module
■ Cyclone III, device support up to 622 Mbps for 64 bit data path; support up to 250
Mbps for 32-bit data path width
■ Configurable data path width—affecting the IP core size and speed—for various
performance requirements and applications:
■ 128 bits
■ 64 bits
■ 32 bits (quarter rate)
■ Supports up to 256 ports
■ Fixed start of packet (SOP) alignment to the most significant byte lane eases
subsequent packet processing
■ First-in first-out (FIFO) buffer status management and indications
■ Configurable FIFO buffer modes
■ Shared buffer with embedded addressing
■ Individual buffers
Table 1–3. Device Family Support
Device Family Support
Arria
®
II GX Preliminary
Arria II GZ Preliminary
Cyclone IV Preliminary
Stratix IV Full
Stratix V Preliminary
Other device families No support
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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