Altera POS-PHY Level 4 IP Core Instrukcja Użytkownika Strona 61
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Chapter 4: Functional Description—Receiver 4–23
Signals
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
Signals
Table 4–5 through Table 4–11 list the I/O signals used in the receiver IP core. The
active low signals are suffixed by
_n
.
Table 4–5. SPI-4.2 Receive Interface
Signal Direction Clock Domain Description
rdclk
LVDS Clock
Input
rdclk
SPI-4.2 differential receive clock. Double-data rate clock
synchronous to
rctl
and
rdat
.
rctl
LVDS Input
SPI-4.2 differential receive control.
When set to a logic 1, the word on
rdat
is a control word. When
set to a logic 0, the word on
rdat
is a payload word.
rdat[15:0]
LVDS Input
SPI-4.2 differential receive data bus. Bus carries packets/cells or
in-band control words.
rsclk
LVTTL Output
rsclk
(rdint_clk)
SPI-4.2 receive status clock. This signal uses a regular LVTTL
data pin instead of a dedicated output clock pin. Derived from
rdclk
. Active if
rdclk
is active.
rstat[1:0]
LVTTL Output
SPI-4.2 receive status channel. Indicates the downstream
device’s FIFO buffers’ fill level to the upstream device’s scheduler.
Table 4–6. Global
Signal Direction Clock Domain Description
rdint_clk
Output
rdint_clk
Derived from
rdclk
. Signals infixed with
_rd_
are
synchronous to this clock. Active if
rdclk
is active.
rxsys_clk
Input
rxsys_clk
System clock. Signals infixed with
_ry_
are synchronous to
this clock.
rxreset_n
Input Asynchronous
Active low asynchronous reset to all internal logic, including
Atlantic FIFO buffers. Refer to “Reset Structure” on
page 4–12.
rxinfo_aot[12:0]
Output Static
Fixed output information signal that contains the current
AOT number for the release.
stat_rx_pll_locked
Output Asynchronous
Locked signal directly from fast PLL in
ALTVDS
for full rate
variations, or enhanced PLL in quarter-rate variations.
ctl_rx_pll_areset
Input Asynchronous
Asynchronous reset signal directly to fast PLL in
ALTVDS
for
full rate variations, or enhanced PLL in quarter-rate
variations.
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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