Altera POS-PHY Level 4 IP Core Instrukcja Użytkownika Strona 95
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Chapter 5: Functional Description—Transmitter 5–25
Avalon-MM Interface Register Map
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
1 If the hitless bandwidth repositioning (
HBWR
) register is not enabled, the
CALM1
,
CALLEN1
,
CALMEM_DAT
registers become reserved.
1 Only change the
CALM0
,
CALLEN0
,
CALMEM_DAT0
registers when the
DISABLED
register is
equal to 1, or when the
CALSEL_ACT
register is equal to 1. Only change the
CALM1
,
CALLEN1
,
CALMEM_DAT1
registers when the
DISABLED
register is equal to 1, or when the
CALSEL_ACT
register is equal to 0.
Table 5–10. Avalon-MM Interface Register Map
Address Bits Name Type Description
0
12:0
AOT_ID
Read only status AOT code
15:13
BLOCK_ID
Read only status Block ID
1
0
HBWR_EN
Read write control
HBWR_EN
enables the calendar select word in the status
frame.
1
RSFRM
Read write control
RSFRM
disables the status finite state machine. This forces
stat_ts_sync
low and
stat_ts_disabled
high at the end
of the current status frame. Regular behavior eventually
resumes after this bit is cleared. The value of the register is
OR
ed with the
ctl_ts_rsfrm
input.
This bit resets to one. Therefore, you must reprogram the
calendar and clear this bit whenever the IP core is reset.
2
RESERVED
Reserved Reserved.
3
CALSEL_ACT
Read only status
CALSEL_ACT
is the active calendar select word. 0=
'b01
,
1=
'b10
4
SYNC
Read only status Mirror of
stat_ts_sync
.
5
DISABLED
Read only status Mirror of
stat_ts_disabled
.
27:0
CALM0
Read write control
CALM
when
CALSEL_ACT
=0.
37:0
CALM1
Read write control
CALM
when
CALSEL_ACT
=1.
49:0
CALLEN0
Read write control
CALLEN
when
CALSEL_ACT
=0.
59:0
CALLEN1
Read write control
CALLEN
when
CALSEL_ACT
=1.
69:0
CALMEM_ADR
Read write indirect
control
Refer to
CALMEM_DAT0
and
CALMEM_DAT1
.
77:0
CALMEM_DAT0
Read write indirect
data
If write, then
CALMEM_ADR
is applied to the write address of
RAM with
CALMEM_DAT0
applied to the write data.
If read, then
CALMEM_ADR
is applied to the read address of
RAM, and resulting read data is captured in
CALMEM_DAT0
.
8 7:0
CALMEM_DAT1
Read write indirect
data
If write, then
CALMEM_ADR
is applied to the write address of
RAM with
CALMEM_DAT1
applied to the write data.
If read, then
CALMEM_ADR
is applied to the read address of
RAM, and resulting read data is captured in
CALMEM_DAT1
.
9..15 —
RESERVED
Reserved Reserved.
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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