Altera POS-PHY Level 4 IP Core Instrukcja Użytkownika Pobierz pdf (Strona 82)

5–12 Chapter 5: Functional Description—Transmitter

Error Flagging and Handling

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

A DIP-2 error occurs when the DIP-2 code locally calculated on the received status

message does not match the DIP-2 received in the status message. If a DIP-2 error

occurs, the

err_ts_dip2

signal is asserted at the end of the calendar sequence for a

single clock cycle.

A framing status error occurs for three regions:

■ When something other than framing is received when the framing pattern is

expected.

■ When an unexpected reserved (

‘b11

) is received.

■ When Hitless B/W reprovisioning is turned on, and a calendar select word is not

‘b01

‘b10

If a framing status error occurs, the

err_ts_frm

signal is asserted for one cycle.

The

stat_ts_sync

signal indicates that the status channel is synchronized. It is

deasserted under the following conditions:

■ At start up, reset, or user

rsfrm

■ Continuous framing is received

■ The MAximum Calendar Length or Calendar Multiplier parameters of the status

channel are improperly configured

■ Continuous DIP-2 errors are received (more than DIP-2 bad threshold)

Two 4-bit inputs,

ctl_ts_sync_good_theshold

and

ctl_ts_sync_bad_theshold

control the

stat_ts_sync

signal.

The

stat_ts_sync

signal is asserted when a programmed

good_level

number of

consecutive, non-errored calendar sequences is received. When

stat_ts_sync

asserted, the IP core sends status normally, based on the received status. The

transmitter’s credit and scheduling logic can send normal traffic (refer to Figure 5–6).

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