Altera Stratix IV E FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 19)

Chapter 2: Board Components 2–11

MAX II CPLD EPM2210 System Controller

May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual

MAX_PHASE_CLK0 2.5-V J4 — U30.A8

Power regulator 0 degrees phase

control

MAX_PHASE_CLK180 2.5-V K1 — U33.B9

Power regulator 180 degrees phase

control

MAX_TO_STRATIX4 2.5-V H1 K1 — Optional pin for user function

MAX_USER

2.5-V G12 — D19

User-defined LED (labeled as

USER_1

USER_2

on the board)

MAX_WEn 2.5-V K15 K28 — FSM bus MAX II write enable

OVERTEMP 2.5-V M4 — Q1 Fan speed control

OVERTEMPn 2.5-V E7 — U18.9

Temperature monitor

over-temperature indicator

PGM0 2.5-V N13 — SW5.1 Rotary switch input

PGM1 2.5-V P15 — SW5.2 Rotary switch input

PGM2 2.5-V M14 — SW5.4 Rotary switch input

PGM3 2.5-V N16 — SW5.8 Rotary switch input

PHASE0 2.5-V C13 — U49.4 Power clock 0 degrees

PHASE90 2.5-V B16 — U49.5, U36.A8 Power clock 90 degrees

PHASE180 2.5-V C12 — U49.6, U29.A8 Power clock 180 degrees

PHASE270 2.5-V A15 — U49.7, U6.A8 Power clock 270 degrees

RESET_CONFIGn 2.5-V R16 — S1

Force FPGA configuration

push-button switch

SENSE_ADC_F0 2.5-V E2 — U44.2 Power monitor frequency

SENSE_CS0n 2.5-V F5 — U43.3 Power monitor 0 chip select

SENSE_CS1n 2.5-V F2 — U43.2 Power monitor 1 chip select

SENSE_SCK 2.5-V E1 — U44.5 Power monitor SPI clock

SENSE_SDI 2.5-V F4 — U44.4 Power monitor SPI data in

SENSE_SDO 2.5-V F3 — U44.3 Power monitor SPI data out

SSRAM_GWn 2.5-V E11 — U3.B7 FSM bus SSRAM global write enable

SSRAM_MODE 2.5-V D11 — U3.R1

FSM bus SSRAM burst sequence

selection

SSRAM_ZZ 2.5-V A13 — U3.H11 FSM bus SSRAM power sleep mode

SYS_RESETn 2.5-V M9 U31 S5 User-defined reset

TSENSE_ALERTN 2.5-V J5 — U18.11 Temperature monitor alert

TSENSE_SMB_CLK 2.5-V L3 — U18.14, U21.6 Temperature monitor SMB clock

TSENSE_SMB_DATA 2.5-V N1 — U18.12, U21.7 Temperature monitor SMB data

VDDQ_QDRII_PG 2.5-V A9 — U16.7 I/O supply

Table 2–5. MAX II CPLD EPM2210 System Controller Device (U10) Pin-Out (Part 5 of 5)

Schematic Signal Name

I/O

Standard

EPM2210

Pin Number

Stratix IV E

Device

Pin Number

Other

Connections

Description

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 71 72

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