Altera Stratix IV E FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 48)

2–40 Chapter 2: Board Components

Components and Interfaces

Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation

J9.67 LVDS TX bit 3n or CMOS bit 18 HSMB_TX_D_N3

LVDS or 2.5-V

T4 —

J9.68 LVDS RX bit 3n or CMOS bit 19 HSMB_RX_D_N3 P1 —

J9.71 LVDS TX bit 4 or CMOS bit 20 HSMB_TX_D_P4 R10 —

J9.72 LVDS RX bit 4 or CMOS bit 21 HSMB_RX_D_P4 M1 —

J9.73 LVDS TX bit 4n or CMOS bit 22 HSMB_TX_D_N4 R9 —

J9.74 LVDS RX bit 4n or CMOS bit 23 HSMB_RX_D_N4 N1 —

J9.77 LVDS TX bit 5 or CMOS bit 24 HSMB_TX_D_P5 R7 —

J9.78 LVDS RX bit 5 or CMOS bit 25 HSMB_RX_D_P5 L2 —

J9.79 LVDS TX bit 5n or CMOS bit 26 HSMB_TX_D_N5 R6 —

J9.80 LVDS RX bit 5n or CMOS bit 27 HSMB_RX_D_N5 L1 —

J9.83 LVDS TX bit 6 or CMOS bit 28 HSMB_TX_D_P6 N9 —

J9.84 LVDS RX bit 6 or CMOS bit 29 HSMB_RX_D_P6 K4 —

J9.85 LVDS TX bit 6n or CMOS bit 30 HSMB_TX_D_N6 N8 —

J9.86 LVDS RX bit 6n or CMOS bit 31 HSMB_RX_D_N6 K3 —

J9.89 LVDS TX bit 7 or CMOS bit 32 HSMB_TX_D_P7 M7 —

J9.90 LVDS RX bit 7 or CMOS bit 33 HSMB_RX_D_P7 J4 —

J9.91 LVDS TX bit 7n or CMOS bit 34 HSMB_TX_D_N7 M6 —

J9.92 LVDS RX bit 7n or CMOS bit 35 HSMB_RX_D_N7 J3 —

J9.95

LVDS or CMOS clock out 1 or

CMOS bit 36

HSMB_CLK_OUT_P1

P6 —

J9.96

LVDS or CMOS clock in 1 or

CMOS bit 37

HSMB_CLK_IN_P1

U2 —

J9.97

LVDS or CMOS clock out 1 or

CMOS bit 38

HSMB_CLK_OUT_N1

P5 —

J9.98

LVDS or CMOS clock in 1 or

CMOS bit 39

HSMB_CLK_IN_N1

U1 —

J9.101 LVDS TX bit 8 or CMOS bit 40 HSMB_TX_D_P8 L7 —

J9.102 LVDS RX bit 8 or CMOS bit 41 HSMB_RX_D_P8 H2 —

J9.103 LVDS TX bit 8n or CMOS bit 42 HSMB_TX_D_N8 L6 —

J9.104 LVDS RX bit 8n or CMOS bit 43 HSMB_RX_D_N8 J1 —

J9.107 LVDS TX bit 9 or CMOS bit 44 HSMB_TX_D_P9 L5 —

J9.108 LVDS RX bit 9 or CMOS bit 45 HSMB_RX_D_P9 G2 —

J9.109 LVDS TX bit 9n or CMOS bit 46 HSMB_TX_D_N9 L4 —

J9.110 LVDS RX bit 9n or CMOS bit 47 HSMB_RX_D_N9 H1 —

J9.113 LVDS TX bit 10 or CMOS bit 48 HSMB_TX_D_P10 K6 —

J9.114 LVDS RX bit 10 or CMOS bit 49 HSMB_RX_D_P10 F1 —

J9.115 LVDS TX bit 10n or CMOS bit 50 HSMB_TX_D_N10 K5 —

J9.116 LVDS RX bit 10n or CMOS bit 51 HSMB_RX_D_N10 G1 —

J9.119 LVDS TX bit 11 or CMOS bit 52 HSMB_TX_D_P11 J7 —

Table 2–41. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board

Reference

Description Schematic Signal

Name

I/O Standard

Stratix IV E

Device

Pin Number

Other

Connections

1 2 ... 43 44 45 46 47 48 49 50 51 52 53 ... 71 72

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Altera Stratix IV E FPGA Development Board Instrukcja Użytkownika Strona 48

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