Altera Stratix IV E FPGA Development Board Instrukcja Użytkownika Strona 65
- Strona / 72
- Spis treści
- BOOKMARKI
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- 1–2 Chapter 1: Overview 6
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- Handling the Board 8
- 2. Board Components 9
- Board Overview 10
- I/O Resources 14
- Configuration 20
- Figure 2–4. JTAG Chain 21
- Flash Memory Programming 22
- Status Elements 23
- Setup Elements 25
- MAX II DIP Switch 26
- User DIP Switch 27
- Clock Enable DIP Switch 27
- JTAG Chain Jumpers 28
- On-Board Memory Headers 29
- Rotary Switch 30
- Stratix IV E FPGA Clocks 30
- EP4SE530H35 31
- General User Input/Output 32
- User-Defined LEDs 33
- General User-Defined LEDs 34
- HSMC User-Defined LEDs 34
- Seven-Segment LED Display 35
- Character LCD 36
- Graphics LCD 38
- 10/100/1000 Ethernet 39
- Components and Interfaces 40
- Embedded USB-Blaster 41
- High-Speed Mezzanine Cards 41
- ■ QDR II+ 50
- ■ RLDRAM II CIO 50
- QDR II+ SRAM 55
- RLDRAM II CIO 57
- Power Supply 65
- Power Distribution System 66
- Power Measurement 67
- Notes to Table 2–55: 68
- A. Board Revision History 69
- Typographic Conventions 72
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