Altera Stratix IV E FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 6)

1–2 Chapter 1: Overview

Board Component Blocks

Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation

■ MAX

II EPM2210F256C3N CPLD in the 256-pin FBGA package

■ 2.5-V core power

■ FPGA configuration circuitry

■ MAX

II CPLD EPM2210 System Controller and Flash fast passive parallel (FPP)

configuration

■ On-board USB-Blaster

for use with the Quartus

II Programmer

■ On-Board ports

■ USB 2.0 – FTDI 12-Mbps PHY

■ One Gigabit Ethernet port

■ Two HSMC expansion ports

■ On-Board memory

■ 2-gigabytes (GB) DDR3 SDRAM DIMM with a 72-bit data bus

■ 72-megabits (Mb) QDR II+ SRAM with a 18-bit data bus

■ 576-Mb RLDRAM II combined input/output (CIO) with a 36-bit data bus

■ 18-Mb Synchronous Static Random Access Memory (SSRAM) with a 36-bit

data bus

■ 512-Mb Flash with a 16-bit data bus

■ On-Board clocking circuitry

■ Five on-board oscillators

■ 50-MHz oscillator (one single-ended input to the FPGA and Max II CPLD)

■ 66-MHz oscillator (two differential inputs to the FPGA)

■ 100-MHz oscillator (one differential inputs to the FPGA)

■ 100-MHz oscillator (one single-ended input to the Max II CPLD)

■ 125-MHz oscillator (two differential inputs to the FPGA)

■ SMA connectors for external clock input

■ SMA connector for clock output

■ HSMC input and output ports

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Altera Stratix IV E FPGA Development Board Instrukcja Użytkownika Strona 6