Altera Stratix IV E FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 44)

2–36 Chapter 2: Board Components

Components and Interfaces

Stratix IV E FPGA Development Board Reference Manual May 2011 Altera Corporation

J19.47 LVDS TX bit 0 or CMOS bit 4

HSMA_TX_D_P0

LVDS or 2.5-V

AC11 —

J19.48 LVDS RX bit 0 or CMOS bit 5

HSMA_RX_D_P0

AJ4 —

J19.49 LVDS TX bit 0n or CMOS bit 6

HSMA_TX_D_N0

AB10 —

J19.50 LVDS RX bit 0n or CMOS bit 7

HSMA_RX_D_N0

AJ3 —

J19.53 LVDS TX bit 1 or CMOS bit 8

HSMA_TX_D_P1

AC9 —

J19.54 LVDS RX bit 1 or CMOS bit 9

HSMA_RX_D_P1

AG4 —

J19.55 LVDS TX bit 1n or CMOS bit 10

HSMA_TX_D_N1

AC8 —

J19.56 LVDS RX bit 1n or CMOS bit 11

HSMA_RX_D_N1

AG3 —

J19.59 LVDS TX bit 2 or CMOS bit 12

HSMA_TX_D_P2

AH5 —

J19.60 LVDS RX bit 2 or CMOS bit 13

HSMA_RX_D_P2

AM2 —

J19.61 LVDS TX bit 2n or CMOS bit 14

HSMA_TX_D_N2

AH4 —

J19.62 LVDS RX bit 2n or CMOS bit 15

HSMA_RX_D_N2

AM1 —

J19.65 LVDS TX bit 3 or CMOS bit 16

HSMA_TX_D_P3

AE8 —

J19.66 LVDS RX bit 3 or CMOS bit 17

HSMA_RX_D_P3

AL2 —

J19.67 LVDS TX bit 3n or CMOS bit 18

HSMA_TX_D_N3

AE7 —

J19.68 LVDS RX bit 3n or CMOS bit 19

HSMA_RX_D_N3

AL1 —

J19.71 LVDS TX bit 4 or CMOS bit 20

HSMA_TX_D_P4

AF6 —

J19.72 LVDS RX bit 4 or CMOS bit 21

HSMA_RX_D_P4

AJ2 —

J19.73 LVDS TX bit 4n or CMOS bit 22

HSMA_TX_D_N4

AF5 —

J19.74 LVDS RX bit 4n or CMOS bit 23

HSMA_RX_D_N4

AK1 —

J19.77 LVDS TX bit 5 or CMOS bit 24

HSMA_TX_D_P5

AD7 —

J19.78 LVDS RX bit 5 or CMOS bit 25

HSMA_RX_D_P5

AH2 —

J19.79 LVDS TX bit 5n or CMOS bit 26

HSMA_TX_D_N5

AD6 —

J19.80 LVDS RX bit 5n or CMOS bit 27

HSMA_RX_D_N5

AJ1 —

J19.83 LVDS TX bit 6 or CMOS bit 28

HSMA_TX_D_P6

AE6 —

J19.84 LVDS RX bit 6 or CMOS bit 29

HSMA_RX_D_P6

AF4 —

J19.85 LVDS TX bit 6n or CMOS bit 30

HSMA_TX_D_N6

AE5 —

J19.86 LVDS RX bit 6n or CMOS bit 31

HSMA_RX_D_N6

AF3 —

J19.89 LVDS TX bit 7 or CMOS bit 32

HSMA_TX_D_P7

AD4 —

J19.90 LVDS RX bit 7 or CMOS bit 33

HSMA_RX_D_P7

AG1 —

J19.91 LVDS TX bit 7n or CMOS bit 34

HSMA_TX_D_N7

AD3 —

J19.92 LVDS RX bit 7n or CMOS bit 35

HSMA_RX_D_N7

AH1 —

J19.95

LVDS or CMOS clock out 1 or

CMOS bit 36

HSMA_CLK_OUT_P1

V10 —

J19.96

LVDS or CMOS clock in 1 or

CMOS bit 37

HSMA_CLK_IN_P1

W2 —

J19.97

LVDS or CMOS clock out 1 or

CMOS bit 38

HSMA_CLK_OUT_N1

W9 —

Table 2–40. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)

Board

Reference

Description

Schematic Signal

Name

I/O Standard

Stratix IV E

Device

Pin Number

Other

Connections

1 2 ... 39 40 41 42 43 44 45 46 47 48 49 ... 71 72

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Altera Stratix IV E FPGA Development Board Instrukcja Użytkownika Strona 44

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