Altera Stratix IV E FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 55)

Chapter 2: Board Components 2–47

Memory

May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual

Table 2–44 lists the DDR3 component references and manufacturing information.

QDR II+ SRAM

The 72-Mb QDR II+ consists of a single QDR II+ burst-of-4 SRAM, providing 4-MB

memory interface with an 18-bit read data bus and an 18-bit write data bus. The

default I/O voltage for the QDR II+ SRAM and the Stratix IV E FPGA is 1.5 V. Placing

a shunt on jumper J11 provides 1.8 V for VDDQ.

This memory interface is designed to run between 120 MHz, the minimum frequency

for this device, and at a maximum frequency of 400 MHz. The internal bus in the

FPGA is typically 2 or 4 times the width at full rate or half rate respectively. For

example, a 400-MHz 18-bit interface becomes a 200-MHz 72-bit bus.

Table 2–45 lists the QDR II+ SRAM pin assignments, signal names, and functions.

Table 2–44. DDR3 Component References and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

533-MHz 2-GB DDR3

SDRAM UDIMM 256M x72

Micron MT18JSF25672AY-1G1 www.micron.com

J20

DDR3 240-pin DIMM

Socket

AMP/Tyco 1932000-6 www.tycoelectronics.com

Table 2–45. QDR II+ SRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)

Board Reference Description

Schematic Signal Name

I/O Standard

Stratix IV E Device

Pin Number

U11.A9 Address bus

QDRII_A0

1.5-V HSTL Class I

D14

U11.B4 Address bus

QDRII_A1

E14

U11.B8 Address bus

QDRII_A2

A15

U11.C5 Address bus

QDRII_A3

A14

U11.C7 Address bus

QDRII_A4

C14

U11.N5 Address bus

QDRII_A5

U11.N6 Address bus

QDRII_A6

U11.N7 Address bus

QDRII_A7

F14

U11.P4 Address bus

QDRII_A8

U11.P5 Address bus

QDRII_A9

U11.P7 Address bus

QDRII_A10

U11.P8 Address bus

QDRII_A11

E10

U11.R3 Address bus

QDRII_A12

U11.R4 Address bus

QDRII_A13

U11.R5 Address bus

QDRII_A14

U11.R7 Address bus

QDRII_A15

U11.R8 Address bus

QDRII_A16

U11.R9 Address bus

QDRII_A17

F15

U11.A3 Address bus

QDRII_A18

B13

U11.A10 Address bus

QDRII_A19

D15

1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 71 72

Komentarze do niniejszej Instrukcji

Brak uwag

Altera Stratix IV E FPGA Development Board Instrukcja Użytkownika Strona 55

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera Stratix IV E FPGA Development Board