Altera Embedded Peripherals IP Instrukcja Użytkownika Strona 92
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Resource Number
Routing optimization registers 17
Global Signals 2
M10k blocks 0
Total MLAB memory bits 2432
Timing and Fmax
Figure 9-2: Maximum Delays on UART
External Pin
UART IP Core
D Q
Avalon Master
D Q D Q
4 ns
2 ns
8 ns7 ns
COMBI
COMBI
COMBI
The diagram above shows worst case combinatorial delays throughout the UART IP Core. These
estimates are provided by TimeQuest under the following condition:
• Device Family: Series V and above
• Avalon Master connected to Avalon Slave port of the UART with outputs from the Avalon Master
registered
• RS-232 Serial Interface is exported to FPGA Pin
• Clocks for entire system set at 125 MHz
Based on the conditions above the UART IP has an Fmax value of 125 MHz, with the worst delay being
internal register-to-register paths.
The UART has combinatorial logic on both the Input and Output side, with system level implications on
the Input side.
The Input side combinatorial logic (with 7ns delay) goes through the Avalon address decode logic, to the
Read data output registers. It is therefore recommended that Masters connected to the UART IP register
their output signals.
The Output side combinatorial logic (with 2ns delay) goes through the RS-232 Serial Output. There
shouldn’t be any concern on the output side delays though – as it is not a single cycle path. Using the
highest clock divider value of 1, the serial output only toggles once every 16 clocks. This naturally gives a
9-6
Timing and Fmax
UG-01085
2014.24.07
Altera Corporation
16550 UART
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Altera Corporation 10
- Introduction 14
- Device Support 15
- December 16
- Initial release. — 16
- SDRAM Controller Core 17
- Avalon-MM Interface 18
- Off-Chip SDRAM Interface 18
- Memory Profile Page 21
- Timing Page 22
- SDRAM Memory Model 23
- Symptoms of an Untuned PLL 26
- Example Calculation 27
- Parameter Symbol 28
- Value (ns) in -7 Speed Grade 28
- Min. Max 28
- Parameter Symbol Value (ns) 28
- Tri-State SDRAM 31
- Configuration Parameter 32
- Interface 33
- Reset and Clock Requirements 38
- Architecture 38
- Block Level Usage Model 39
- Compact Flash Core 41
- Required Connections 42
- (32-bit Word Address) 54
- Register Name R/W 54
- Bit Description 54
- JTAG UART Core 58
- Read and Write FIFOs 59
- JTAG Interface 59
- Host-Target Connection 59
- Simulation Settings 61
- UART Core 70
- RS-232 Interface 71
- Transmitter Logic 71
- Instantiating the Core 72
- Data Bits, Stop Bits, Parity 73
- Synchronizer Stages 74
- Flow Control 74
- Streaming Data (DMA) Control 74
- Request Description 79
- Bit Name Access Description 81
- May 2008 86
- 16550 UART 87
- Unsupported Features 88
- General Architecture 90
- Configuration Parameters 90
- DMA Support 91
- FPGA Resource Usage 91
- Timing and Fmax 92
- Avalon-MM Slave 93
- Overrun/Underrun Conditions 94
- Hardware Auto Flow-Control 95
- 16550 UART API 98
- Private APIs 99
- UART Device Structure 100
- Figure 9-7: 101
- Driver Examples 102
- UG-01085 103
- 2014.24.07 103
- Document Revision History 106
- SPI Core 107
- txdata 108
- Receiver Logic 109
- Master and Slave Modes 109
- Slave Mode Operation 110
- Multi-Slave Environments 110
- Configuration 111
- Data Register Settings 112
- Timing Settings 112
- Software Programming Model 113
- Software Files 114
- Register Map 115
- # Name Description 116
- Date and 118
- Document 118
- Core Overview 119
- Functional Description 119
- Interrupt Behavior 121
- PIO Core 123
- Data Input and Output 124
- Edge Capture 124
- IRQ Generation 124
- Example Configurations 125
- Input Options 126
- Operation 132
- PCI Lite Core 135
- Avalon-MM Ports 137
- Prefetchable Avalon-MM Master 137
- I/O Avalon-MM Master 138
- PCI Bus Access Slave 138
- Master and Target Performance 139
- Space Indicator 141
- (Bits 1:0) 141
- Description 141
- Avalon-to-PCI Write Request 142
- Ordering of Requests 143
- Send Feedback 145
- PCI Timing Constraint Files 146
- Simulation Considerations 147
- Simulation Flow 149
- MDIO Core 151
- MDIO Frame Format (Clause 45) 152
- MDIO Clock Generation 153
- Interfaces 153
- Parameter 154
- Configuration Registers 154
- On-Chip FIFO Memory Core 156
- Offset Bits Field Description 158
- FIFO Settings 161
- Interface Parameters 161
- Software Control 163
- Field Type Description 164
- Bit(s) Name Description 164
- Software Example 166
- On-Chip FIFO Memory API 167
- Multi-Channel Shared FIFO 176
- Parameters 177
- Address Width 178
- Name Access Reset 180
- Bytes Converter Cores 185
- Feature Property 186
- Transaction 190
- DMA Descriptors 197
- Error Conditions 198
- Signal Type Description 199
- Timeouts 206
- Data Structure 207
- SG-DMA API 208
- Name Description 209
- Overview 217
- Feature Description 217
- Component Interface 220
- Descriptor Slave Port 221
- Component GUI 222
- Byte Lanes 223
- Read and Write Address Fields 224
- Length Field 224
- Sequence Number Field 225
- Read and Write Stride Fields 225
- Control Field 225
- Bit Sub-Field Name Definition 226
- Register Map of mSGDMA 228
- Status Register 229
- Control Register 229
- Bit Name Description 230
- Offset Access 3 2 1 0 230
- Unsupported Feature 231
- DMA Controller Core 232
- Setting Up DMA Transactions 233
- Advanced Options 235
- Video Sync Generator 242
- Parameter Name Description 244
- Horizontal sync pulse 245
- Horizontal front porch 245
- Horizontal blank pixels 245
- Pixel Converter 246
- Interval Timer Core 249
- Counter Size 251
- Hardware Options 251
- Bit Name R/W/C Description 255
- Mutex Core 258
- Mutex API 260
- Mailbox Core 264
- Mailbox API 267
- Functional Blocks 273
- Register Maps 275
- Run-time Initialization 285
- Board Support Package 285
- VIC IRQ RRS RIL 291
- November 293
- Altera FPGA 294
- Core Behavior 295
- System ID Core 298
- Performance Counter Core 301
- Global Counter 302
- Using the Performance Counter 304
- Name (1) Meaning 305
- Performance Counter API 306
- PERF_START_MEASURING() 307
- PERF_STOP_MEASURING() 307
- PERF_BEGIN() 307
- PERF_END() 308
- PLL Cores 312
- Registers 313
- PLL Core 313
- ALTPLL Megafunction 313
- Instantiating the PLL Core 314
- Altera MSI to GIC Generator 320
- Interrupt Servicing Process 321
- Registers of Component 322
- Altera SMBus Core Interface 324
- Component Parameterization 326
- Frequency Register 331
- 32-bit Counter 332
- Software Access 334
- Implementation Details 335
- IP Caveats 336
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