Altera SDI II MegaCore Instrukcja Użytkownika Pobierz pdf (Strona 19)

Simulator Supported Platform Supported Language

Aldec Riviera-PRO Linux Verilog

To simulate the design using the ModelSim-SE or ModelSim-Altera simulator, follow these steps:

1. Start the simulator.

2. On the File menu, click Change Directory > Select <variation name>_example_design/simulation/

verilog/mentor (for Verilog HDL language) or _example_design/simulation/vhdl/mentor (for

VHDL language).

3. Run the provided run_sim.tcl script. This file compiles the design and runs the simulation automati‐

cally. It provides a pass/fail indication on completion.

To simulate the design using the VCS/VCS MX simulator (in Linux), follow these steps:

1. Start the VCS/VCS MX simulator.

2. On the File menu, click Change Directory > Select <variation name>_example_design/sdi_ii/

simulation/verilog/synopsys.

3. Run the provided run_vcs.sh (in VCS) or run_vcsmx.sh (in VCSMX) script. This file compiles the design

and runs the simulation automatically. It provides a pass/fail indication on completion.

To simulate the design using the Aldec Riviera-PRO simulator, follow these steps:

1. Start the Aldec Riviera-PRO simulator.

2. On the File menu, click Change Directory > Select <variation name>_example_design/sdi_ii/

simulation/verilog/aldec.

3. Run the provided run_riviera.tcl script. This file compiles the design and runs the simulation automati‐

cally. It provides a pass/fail indication on completion.

Timing Violation

After you create a new project, the Quartus II software generates a Quartus II Settings File (.qsf). Add the

following assignments to .qsf to avoid timing violation from the synchronizers.

set_instance_assignment -name GLOBAL_SIGNAL OFF -to *|altera_reset_synchron-

izer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out

Compiling the SDI II IP Core Design

To compile your design, click Start Compilation on the Processing menu in the Quartus II software. You

can use the generated .qip file to include relevant files into your project.

You can find the design examples of the SDI II IP core in the <variation name>_example_design/

example_design/<variation name>_example_design directory. For the design example illustrations, refer

to the Design Examples section.

Note:

To create a new project using the generated design example, follow the steps in the Creating a New

Quartus II Project section and add the design example .qip file in step 4.

Related Information

• Creating a New Quartus II Project on page 3-2

3-4

Timing Violation

UG-01125

2015.05.04

Altera Corporation

SDI II IP Core Getting Started

Send Feedback

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 88 89

Komentarze do niniejszej Instrukcji

Brak uwag

Altera SDI II MegaCore Instrukcja Użytkownika Strona 19

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera SDI II MegaCore