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Oceniono. / 5. Na podstawie oceny klientów
Signal Width Direction Description
rx_format
5 Output Indicates the format for the received video transport.
• SMPTE259M 525i = 00000
• SMPTE259M 625i = 00001
• SMPTE274M 1080i30/60/59.94 = 00100
• SMPTE274M 1080i25/50 = 00101
• SMPTE274M 1080p24/23.98 = 00110
• SMPTE296M 720p60/59.94 = 00111
• SMPTE296M 720p50 = 01000
• SMPTE296M 720p30/29.97 = 01001
• SMPTE296M 720p25 = 01010
• SMPTE296M 720p24/23.98 = 01011
• SMPTE274M 1080p30/29.97/60/59.94 = 01100
• SMPTE274M 1080p25/50 = 01101
• SMPTE274M 1080i24 = 01110
• SMPTE ST 2036 UHDTV1 (3840×2160P) 24 = 01111
• SMPTE ST 2036 UHDTV1 (3840x2160P) 25/50 = 10000
• SMPTE ST 2036 UHDTV1 (3840x2160P) 30/60 = 10001
• Undetectable format, revert to default value: 11111
• Others = Reserved
The format represents only the video transport format; not the
picture format. For example, when 1080p50 video is transported
on HD-SDI dual link, the video transport format is 1080i50.
To differentiate between video format with 1 and 1/1.001 rate,
you have to also refer to the rx_clkout_is_ntsc_paln output
signal. For example, if rx_format = 00100, rx_clkout_is_ntsc_
paln = 1, then the format for the received video is 1080i59.94.
Otherwise, it is 1080i60.
To differentiate between video format across HD and 3G
interfaces, you have to also refer to the rx_std output signal. For
example, if rx_format = 1100 and rx_clkout_is_ntsc_paln =
0, rx_std = 01, then the received video format is 1080p30. If the
rx_std = 11 or 10, then the received video format is 1080p60.
Note:
For 3G-SDI, HD-SDI dual link, and triple standard
modes, you may get an inconsistent format detection
if the incoming data does not include a payload ID
packet.
rx_eav
1S Output Receiver output that indicates current TRS is EAV. This signal is
asserted at the fourth word of TRS, which is the XYZ word.
rx_trs
1S Output Receiver output that indicates current word is TRS. This signal is
asserted at the first word of 3FF 000 000 TRS.
rx_align_locked
1 Output Alignment locked, indicating that a TRS has been spotted and
word alignment is performed.
4-34
SDI II IP Core Signals
UG-01125
2015.05.04
Altera Corporation
SDI II IP Core Functional Description
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- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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