Altera SDI II MegaCore Instrukcja Użytkownika Pobierz pdf (Strona 42)

Related Information

• Reconfiguration Management on page 3-16

• Modifying the Reconfiguration Management on page 3-20

Reconfiguration Router Signals

Table below lists the signals for the reconfiguration router.

Table 3-12: Reconfiguration Router Top Level Signals

The listed signals are exported at the top level of the design example. Other signals—that are not exported—

connect within the design example entity.

Note: These signals are available only when you use the Dynamic TX clock switching feature.

Refer to Dynamic TX Clock Switching for usage requirements.

Signal Width Directio

Description

ch1_<direction>_tx_start_reconfig

1 Input Dynamic reconfiguration request signal

for TX PLL dynamic switching at

transmitter or duplex instance at channel

ch1_<direction>_tx_pll_sel

1 Input TX PLL select signal for TX PLL dynamic

switching at transmitter or duplex

instance at channel 1. This signal is also

connected to xcvr_refclk_sel signal of

the SDI instance.

ch1_<direction>_tx_reconfig_done

1 Output Dynamic reconfiguration acknowledge

signal for TX PLL dynamic switching at

transmitter or duplex instance at channel

Related Information

• Reconfiguration Router on page 3-17

• Modifying the Reconfiguration Router on page 3-21

UG-01125

2015.05.04

Reconfiguration Router Signals

3-27

SDI II IP Core Getting Started

Altera Corporation

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Altera SDI II MegaCore Instrukcja Użytkownika Strona 42