Altera SDI II MegaCore Instrukcja Użytkownika Pobierz pdf (Strona 55)

Figure 4-17: Altera Native PHY IP Core Setup in Duplex Mode

The Altera Native PHY IP Core does not include an embedded reset controller and an Avalon-MM

interface. This PHY IP core exposes all signals directly as ports. To implement reset functionality for a

new IP core, the transceiver reset controller is required to handle all the transceiver reset sequencing. The

transceiver reset controller controls the embedded reset controller and also manages additional control

options such as automatic or manual reset recovery mode.

Oversample

Transceiver

Control

State Machine

RX PHY Management

& PHY Adapter

20 20

Oversample

Generate

Clock Enable

TX PHY Management

& PHY Adapter

Transceiver

SDI Out

20 20

SDI In

Detect

Video

Standard

Altera

Native PHY

IP Core

Transceiver

Reset Controller

(RX)

Transceiver

Reset Controller

(TX)

Detect

1 & 1/1,001

Rate

Related Information

Altera Transceiver PHY IP Core User Guide

More information about the Altera Native PHY IP Core.

UG-01125

2015.05.04

Transceiver

4-13

SDI II IP Core Functional Description

Altera Corporation

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