Altera SDI II MegaCore Instrukcja Użytkownika Strona 82
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Signal Width Direction Description
reconfig_to_xcvr
70N Input Dynamic reconfiguration input for the hard transceiver, where N
is the reconfiguration interface.
• N = 1 for receiver
• N = 2 for transmitter and bidirectional
Note: Not applicable for Arria 10 devices.
reconfig_from_
xcvr
46N Output Dynamic reconfiguration output for the hard transceiver, where
N is the reconfiguration interface.
• N = 1 for receiver
• N = 2 for transmitter and bidirectional
Note: Not applicable for Arria 10 devices.
reconfig_to_
xcvr_b
70N Input Dynamic reconfiguration input for the hard transceiver (link B),
where N is the reconfiguration interface. For HD-SDI dual link
configuration only.
• N = 1 for receiver
• N = 2 for transmitter and bidirectional
Note: Not applicable for Arria 10 devices.
reconfig_from_
xcvr_b
46N Output Dynamic reconfiguration output for the hard transceiver (link B),
where N is the reconfiguration interface. For HD-SDI dual link
configuration only.
• N = 1 for receiver
• N = 2 for transmitter and bidirectional
Note: Not applicable for Arria 10 devices.
rx_coreclk_is_
ntsc_paln
1 Input Indicates the incoming video rate. For use in all modes except
SD-SDI.
• 0 = PAL rate (when rx_coreclk = 148.5 MHz or rx_
coreclk_hd = 74.25 MHz)
• 1 = NTSC rate (when rx_coreclk = 148.35 MHz or rx_
coreclk_hd = 74.175 MHz)
rx_sdi_start_
reconfig
1 Output Request to start dynamic reconfiguration. Applicable for dual
standard and triple standard modes only.
rx_sdi_reconfig_
done
1 Input Indicates that dynamic reconfiguration has completed.
Applicable for dual standard and triple standard modes only.
rx_clkin_
smpte372
1 Input Clock input for level A to level B and level B to level A
operations.
• Level A to level B = 148.5 MHz or 148.35 MHz
• Level B to level A = 74.25 MHz or 74.175 MHz
4-40
SDI II IP Core Signals
UG-01125
2015.05.04
Altera Corporation
SDI II IP Core Functional Description
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- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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