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Related Information
• Transceiver Reconfiguration Controller on page 3-15
The transceiver reconfiguration controller reconfigures the transceivers. The transceiver reconfiguration
controller in the Arria V, Cyclone V, and Stratix V design examples and the Arria 10 design example is
used differently.
• Modifying the Transceiver Reconfiguration Controller on page 3-19
• Altera Transceiver PHY IP Core User Guide
More information about the transceiver reconfiguration controller frequency range.
Reconfiguration Management Parameters
Table below lists the parameters for reconfiguration management.
Table 3-11: Reconfiguration Management Parameters
Parameter Value Description
NUM_CHS 1 (minimum) Number of channels required to do reconfiguration
FAMILY
• Arria V
• Arria V GZ
• Cyclone V
• Stratix V
Supported device family
DIRECTION
• tx
• rx
• du
Direction of the core selected in the parameter
editor. This parameter affects the logical channel
number assigned in the generated example design.
If you are making any changes to the design, please
ignore this parameter and assign the logical channel
number correctly.
Refer to Expanding to Multiple Channels section to
know how to assign the logical channel number.
VIDEO_STANDARD
• tr
• dl
Current video standard.
Specify dl for HD dual-link or tr for other
standards.
XCVR_TX_PLL_SEL
• 1
• 2
The selected method to perform TX PLL reconfigu‐
ration for dynamic clock switching. Specify 1 to
switch TX PLLs or 2 to switch TX PLL reference
clocks.
The specified value must match the parameter value
you select when you instantiate the core.
Refer to Dynamic TX Clock Switching section to
know more about clock switching.
3-26
Reconfiguration Management Parameters
UG-01125
2015.05.04
Altera Corporation
SDI II IP Core Getting Started
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- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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