Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Instrukcja Użytkownika Strona 142
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Address Name Bit Description HW
Reset
Value
Access
0x0CC
Override AN
Channel
Select
[3:0]
If you set the value of the Override AN Channel
Enable register field (0xC0[6]) to the value of 1,
then while 0xC0[6] has the value of 1, the value
in this register field (0xCC[3:0])overrides the
master channel you set with the Auto-Negotia‐
tion Master parameter.
This register field has the following valid values:
• 4'b0001: Selects Lane 0
• 4'b0010: Selects Lane 1
• 4'b0100: Selects Lane 2
• 4'b1000: Selects Lane 3
All other values are invalid. The new master
channel is encoded with one-hot encoding.
4'b0
RW
0x0D1
Restart Link
training,
Lane 1
[1]
When set to 1, resets the 40GBASE-KR4 start-up
protocol. When set to 0, continues normal
operation. This bit self clears. Refer to the state
variable mr_restart_training as defined in
Clause 72.6.10.3.1 and 10GBASE-KR PMD
control register bit (1.150.0) in IEEE Std 802.3ap-
2007.
Register bit 0xD1[0] refers to Lane 0. This bit is
the equivalent of register 0xD1[0] for Lane 1.
(Refer to 10GBASE-KR PHY Register
Definitions).
1'b0
RW
Restart Link
training,
Lane 2
[2]
This bit is the equivalent of register 0xD1[0] for
Lane 2. (Refer to 10GBASE-KR PHY Register
Definitions).
1'b0
RW
Restart Link
training,
Lane 3
[3]
This bit is the equivalent of register 0xD0[1] for
Lane 3. (Refer to 10GBASE-KR PHY Register
Definitions).
1'b0
RW
UG-01088
2014.12.15
40GBASE-KR4 Registers
3-95
Functional Description
Altera Corporation
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- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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