Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Instrukcja Użytkownika Strona 23
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Getting Started
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The following sections explain how to install, parameterize, simulate, and initialize the 40-100GbE IP
core:
Installing and Licensing IP Cores on page 2-2
The 40-100GbE IP core is available with the Quartus II software in the Altera MegaCore IP Library.
Specifying the 40-100GbE IP Core Parameters and Options on page 2-3
The 40-100GbE IP core supports a standard customization and generation process from the Quartus II IP
Catalog.. This IP core is not supported in Qsys.
IP Core Parameters on page 2-3
The 40-100GbE parameter editor provides the parameters you can set to configure the 40-100GbE IP core
and simulation testbenches.
Files Generated for the 40-100GbE IP Core on page 2-10
The Quartus II software version 14.1 generates the following output for your 40-100GbE IP core.
Simulating the IP Core on page 2-10
Integrating Your IP Core in Your Design on page 2-11
40-100GbE IP Core Testbenches on page 2-14
Altera provides a testbench and an example design with most variations of the 40-100GbE IP core. The
testbench is available for simulation of your IP core, and the example design targets a C2 speed grade
device and can be run on hardware. You can run the testbench to observe the IP core behavior on the
various interfaces in simulation.
Simulating the 40-100GbE IP Core With the Testbenches on page 2-20
Compiling the Full Design and Programming the FPGA on page 2-24
Initializing the IP Core on page 2-24
Related Information
Managing Quartus II Projects
Refer to the "Integrating IP Cores" section of this Quartus II Handbook chapter for more information
about generating an Altera IP core and integrating it in your Quartus II project.
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- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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